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ht82a623r/ht82a6208/ht82a6216 a/d type full speed usb 8-bit mcu with spi rev. 1.30 1 january 14, 2011 features operating voltage: - vdd (mcu) f sys = 6mhz: 2.2v~5.5v f sys = 12mhz: 3.0v~5.5v - ubus (usb bus voltage): 4.5v~5.5v - vcc (ht82a6208 & ht82a6216 for flash): 2.8v~3.6v 4k15 bits program memory 1608 bits data memory ram ht82a6208: 8m1 bits flash memory structure ht82a6216: 16m 1 bits or 8mx2 bits flash memory structure 32 bidirectional i/o lines usb 2.0 full speed compatible one external interrupt input shared with i/o line two 16-bit programmable timer/event counters with overflow interrupt two spi interfaces (master and slave mode) shared with pa0~pa3, pb0~pb3 total of 6 interrupts - ext, timer0, timer1, spia, spib, usb flash serial peripheral interface compatible - mode0 and mode3 82886081bit flash memory structure - ht82a6208 167772161bit or 8388608x2bit flash memory structure - ht82a6216 256 equal sector with 4k byte each for flash memory structure- ht82a6208 512 equal sector with 4k byte each for flash memory structure- ht82a6216 flash memory input data format: 1-byte command code flash memory block lock protection single power supply operation watchdog timer function 32768hz real time clock power down and wake-up functions to reduce power consumption 16 channel 12-bit resolution a/d converter 2-channel 8-bit pwm output shared with two i/o lines up to 0.33ms instruction cycle with 12mhz system clock at v dd =5v max. 4 endpoints supported - endpoint 0 included all endpoints support interrupt, & bulk transfer endpoint 0 supports control, interrupt and bulk transfer all endpoints except endpoint 0 can be configured as 8, 16, 32, 64 fifo size endpoint 0 has 8 byte fifo total fifo size: 64+8 bytes (ram0: 48 bytes; ram1:16 bytes, 8 bytes for endpoint0) 2.2v 5% lvd 6-level subroutine nesting bit manipulation instruction table read instructions 63 powerful instructions all instructions executed in one or two instruction cycles low voltage reset function wide range of available package types technical document application note - ha0075e mcu reset and oscillator circuits application note
selection table the following table summarises the main features of each device. part no. vdd vcc program memory data memory flash memory i/o timer a/d pwm spi stack package 16-bit rtc ht82a623r 2.2v~ 5.5v ? 4k 15 1608 ? 32 2 ? 12-bit 16 8-bit 2 2 6 28sop, 28ssop, 48qfn ht82a6208 2.2v~ 5.5v 2.8v~ 3.6v 4k 15 1608 8m 32 2 ? 12-bit 16 8-bit 2 2 6 44/52qfp ht82a6216 16m ht82a623r/ht82a6208/ht82a6216 rev. 1.30 2 january 14, 2011 general description the ht82a623r, ht82a6208 and ht82a6216 are 8-bit high performance risc-like microcontrollers de - signed for usb keyboard, mouse and joystick product applications. the devices are also suitable for use in home appliances, particularly for use in high-level household appliances such as microwave ovens, wash - ing instructions and air conditioner products. the ht82a6208 and ht82a6216 devices also possess an internal 8m or 16m flash memory further enhancing and expanding their application possibilities. the advantages of low power consumption, i/o flexibil - ity, programmable frequency divider, timer functions, oscillator options, multi-channel a/d converter, pulse width modulation function, usb interface, watchdog timer, spi interfaces, power down and wake-up func - tions, enhance the versatility of these devices to suit a wide range of application possibilities. the ht82a6208 contains a 8,388,608 bit serial flash memory, which is configured as 1,048,576 8 internally. the ht82a6216 contains a 16,777,216 bit serial flash memory, which is configured as 2,097,152 8 internally. the ht82a6208/ht82a6216 feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. the three bus signals are a clock in - put (sclk), a serial data input (si), and a serial data output (so). spi access to the device is enabled by the fhcs# input. the device provides a sequential read operation on the whole chip. after a program/erase command is issued, auto pro - gram/ erase algorithms are executed which pro - gram/erase and verify the specified page or byte/sector/block locations. a program command is ex - ecuted on a page (256 bytes) basis, and an erase com - mand is executed on a chip or sector (4k-bytes) or block (64k-bytes) basis. to provide the user with ease of interface, a status reg - ister is included to indicate the status of the device. the status read command can be issued to detect comple - tion status of a program or erase operation via the wip bit. when the ht82a6208/ht82a6216 is not operating and fhcs# is high, it can be put into the standby mode where it will draw less than 10ma/20m a dc current. the ht82a6208/ht82a6216 contains proprietary memory cells, which reliably store memory contents even after 100,000 program and erase cycles.
block diagram ht82a623r/ht82a6208/ht82a6216 rev. 1.30 3 january 14, 2011 s t a c k d a t a m e m o r y i / o p o r t s 8 - b i t t i m e r p r o g r a m m a b l e f r e q u e n c y g e n e r a t o r w a t c h d o g t i m e r o t p p r o g r a m m e m o r y 8 - b i t r i s c m c u c o r e w a t c h d o g t i m e r o s c i l l a t o r r e s e t c i r c u i t i n t e r r u p t c o n t r o l l e r c r y s t a l o s c i l l a t o r 1 l o w v o l t a g e r e s e t a / d c o n v e r t e r p w m g e n e r a t o r s p i a i n t e r f a c e s p i b i n t e r f a c e u s b 2 . 0 f u l l s p e e d e n g i n e u s b 2 . 0 x c v r 3 . 3 v r e g u l a t o r 1 6 - b i t t i m e r c r y s t a l o s c i l l a t o r 2 f l a s h m e m o r y
pin assignment ht82a623r/ht82a6208/ht82a6216 rev. 1.30 4 january 14, 2011 h t 8 2 a 6 2 3 r 4 8 q f n - a 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 p a 0 / s c s a p a 1 / s c l k a p a 2 / s d i a p a 3 / s d o a p a 4 / p w m 0 p a 5 / p w m 1 p a 6 / i n t p a 7 / t m r 0 p c 0 / a n 8 p c 1 / a n 9 p c 2 / a n 1 0 p c 3 / a n 1 1 p b 7 / a n 7 p b 6 / a n 6 p b 5 / a n 5 p b 4 / a n 4 p b 3 / a n 3 / s d o b p b 2 / a n 2 / s d i b p b 1 / a n 1 / s c l k b p b 0 / a n 0 / s c s b p c 7 / a n 1 5 p c 6 / a n 1 4 p c 5 / a n 1 3 p c 4 / a n 1 2 r e s o s c 4 o s c 3 p d 0 / t m r 1 p d 1 p d 2 p d 3 p d 4 p d 5 p d 6 p d 7 n c n c n c v s s v s s o s c 1 o s c 2 n c v 3 3 o d + / c l k d - / d a t a u b u s v d d h t 8 2 a 6 2 0 8 4 4 q f p - a v 3 3 o f h h o l d & v c c n c f h c s # f h s o o s c 2 o s c 1 v s s g n d & g n d & f h w p f h s c l k f h s i p d 7 p d 6 p d 5 p d 4 p d 3 p d 2 p d 1 p d 0 / t m r 1 o s c 3 o s c 4 r e s p b 1 / a n 1 / s c l k b p b 2 / a n 2 / s d i b p b 3 / a n 3 / s d o b p b 4 / a n 4 p b 5 / a n 5 p b 6 / a n 6 p b 7 / a n 7 v d d u b u s d - / d a t a d + / c l k p b 0 / a n 0 / s c s b p c 1 / a n 9 p c 0 / a n 8 p a 7 / t m r 0 p a 6 / i n t p a 5 / p w m 1 p a 4 / p w m 0 p a 3 / s d o a p a 2 / s d i a p a 1 / s c l k a p a 0 / s c s a 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 43 53 63 73 83 94 04 14 24 34 4 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 p b 4 / a n 4 p c 7 / a n 1 5 p c 6 / a n 1 4 p c 5 / a n 1 3 p a 7 / t m r 0 p a 6 / i n t p a 5 / p w m 1 p a 4 / p w m 0 p a 3 / s d o a p a 2 / s d i a p a 1 / s c l k a p a 0 / s c s a p d 5 p d 4 p b 5 / a n 5 p b 6 / a n 6 p b 7 / a n 7 v d d u b u s d - / d a t a d + / c l k v 3 3 o o s c 2 o s c 1 v s s r e s o s c 4 o s c 3 h t 8 2 a 6 2 3 r 2 8 s o p - a / s s o p - a h t 8 2 a 6 2 1 6 4 4 q f p - a v 3 3 o f h h o l d & v c c n c f h c s # f h s o o s c 2 o s c 1 v s s g n d & g n d & f h w p f h s c l k f h s i p d 7 p d 6 p d 5 p d 4 p d 3 p d 2 p d 1 p d 0 / t m r 1 o s c 3 o s c 4 r e s p b 1 / a n 1 / s c l k b p b 2 / a n 2 / s d i b p b 3 / a n 3 / s d o b p b 4 / a n 4 p b 5 / a n 5 p b 6 / a n 6 p b 7 / a n 7 v d d u b u s d - / d a t a d + / c l k p b 0 / a n 0 / s c s b p c 1 / a n 9 p c 0 / a n 8 p a 7 / t m r 0 p a 6 / i n t p a 5 / p w m 1 p a 4 / p w m 0 p a 3 / s d o a p a 2 / s d i a p a 1 / s c l k a p a 0 / s c s a 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 43 53 63 73 83 94 04 14 24 34 4 p c 4 / a n 1 2 p c 3 / a n 1 1 p c 2 / a n 1 0 p c 1 / a n 9 p c 0 / a n 8 p a 7 / t m r 0 p a 6 / i n t p a 5 / p w m 1 p a 4 / p w m 0 p a 3 / d s o a p a 2 / s d i a p a 1 / s c l k a p a 0 / s c s a 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 3 4 3 5 3 6 3 7 3 8 3 9 4 84 95 05 15 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 h t 8 2 a 6 2 0 8 h t 8 2 a 6 2 1 6 5 2 q f p - a 4 04 14 24 34 4 4 54 64 7 p c 5 / a n 1 3 p c 6 / a n 1 4 p c 7 / a n 1 5 p b 0 / a n 0 / s c s b p b 1 / a n 1 / s c l k b p b 2 / a n 2 / s d i b p b 3 / a n 3 / s d o b p b 4 / a n 4 p b 5 / a n 5 p b 6 / a n 6 p b 7 / a n 7 v d d u b u s p d 7 p d 6 p d 5 p d 4 p d 3 p d 2 p d 1 p d 0 / t m r 1 o s c 3 o s c 4 r e s n c n c d - / d a t a d + / c l k v 3 3 o n c f h c s # f h s o v c c & f h h o l d o s c 2 o s c 1 v s s & v s s & v s s g n d & g n d & f h w p f h s c l k f h s i
pin description pin name i/o options description pa0/scsa pa1/sclka pa2/sdia pa3/sdoa pa4/pwm0 pa5/pwm1 pa6/int pa7/tmr0 i/o pull-high wake-up nmos or cmos bidirectional 8-bit input/output port. each pin can be configured as a wake-up input by a configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine if the pins have pull-high resistors. the intb and tmr0 pins are pin-shared with pa6 and pa7 respectively. pa0~pa3 are shared with the spia function. pa4~pa5 are shared with pwm0 and pwm1. pb0/an0/scsb pb1/an1/sclkb pb2/an2/sdib pb3/an3/sdob pb4/an4 pb5/an5 pb6/an6 pb7/an7/vddio i/o pull-high wake-up pb7/vddio pb0~pb6 with vddio bidirectional 8-bit input/output port. each nibble, pb0~pb3 and pb4~pb7 pin can be configured as a wake-up input by a configuration option. soft - ware instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine if the pins have pull-high resistors. pb is pin shared with the a/d inputs. once a pb line is selected as an a/d input using software control, the i/o function and pull-high resistor are dis - abled automatically. pb7 can be configured as a normal i/o or a vddio pin by configuration option. the power supply for pins pb0~pb6 can be set to either vdd or vddio by configuration options. pb0~pb3 are shared with spib. pc0/an8~ pc7/an15 i/o pull-high wake-up bidirectional 8-bit input/output port. each nibble, pc0~pc3 and pc4~pc7 pin can be configured as a wake-up input by a configuration option. soft - ware instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine if the pins have pull-high resistors. pc is pin shared with the a/d inputs. once a pc line is selected as an a/d input using software control, the i/o function and pull-high resistor are dis - abled automatically. pd0/tmr1 pd1~pd7 i/o pull-high wake-up bi-directional 8-bit input/output port. each nibble, pd0~pd3 and pd4~pd7 pin can be configured as a wake-up input by a configuration option. soft- ware instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine if the pins have pull-high resistors. the tmr1 pin is shared with pd0. d-/data i/o ? usbd- line d+/clk i/o ? usbd+ line v33o o ? 3.3v regulator output ubus ? ? usb sie vdd osc1 osc2 i o ? osc1, osc2 are connected to an external 6mhz or 12mhz crystal/reso - nator, determined by software instructions, for the internal system clock osc3 osc4 i o ? real time clock oscillator. osc3, osc4 are connected to a 32768hz crys - tal oscillator for timing purposes or to a system clock source (depending on the options). no built-in capacitor. res i ? schmitt trigger reset input. active low vdd ? ? positive power supply of mcu except for usbsie fhcs# i ? flash memory chip select fhsi i ? flash memory serial data input fhso o ? flash memory serial data output fhsclk i ? flash memory clock input fhhold i ? flash memory hold, to pause the device without deselecting the device fhwp i ? flash memory write protection vcc ? ? ht82a6208 and ht82a6216 flash memory positive power supply note: the pin description reflects the situation of the largest package, smaller package types may not contain all pins described in the table. ht82a623r/ht82a6208/ht82a6216 rev. 1.30 5 january 14, 2011
absolute maximum ratings supply voltage ...........................v ss -0.3v to v ss +6.0v storage t emperature ............................ -50c to 125c input voltage..............................v ss -0.3v to v dd +0.3v operating t emperature...............................0 c to 70c i ol total ..............................................................150ma i oh total............................................................ -100ma t otal power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under 2 absolute maximum ratings 2 may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd mcu operating voltage ? f sys =6mhz 2.2 ? 5.5 v f sys =12mhz 3.0 ? 5.5 v v cc ht82a6208 and ht82a6216 flash memory operating voltage ? ? 2.8 3.3 3.6 v ubus usb sie operating voltage ? ? 4.5 ? 5.5 v i dd1 operating current 5v no load, f sys =12mhz, adc off, dac off ? 8 ? ma i dd2 operating current 5v no load, f sys =12mhz, adc on, dac on ? 12 ? ma i sus suspend current 5v no load, system halt, usb transceiver and 3.3v regulator on ? 330 500 ma i stb standby current (wdt disabled) 5v no load ,system halt, ps mode, set susp2 [ucc.4] ? ? 10 ma v il1 input low voltage for i/o ports 5v ? 0 ? 0.3v dd v v ih1 input high voltage for i/o ports 5v ? 0.7v dd ? v dd v v il2 input low voltage (res ) 5v ? 0 ? 0.4v dd v v ih2 input high voltage (res ) 5v ? 0.8v dd ? v dd v v lvr0 low voltage reset 5v ? 1.9 2.0 2.1 v v v33o 3.3v regulator output 5v i v33o =-5ma 3.0 3.3 3.6 v v ad 12-bit a/d input voltage ? ? 0 ? v dd v v os offset error ? ? -2 ? 2 mv v lvd low voltage detect ? ? 2.1 2.2 2.3 v i ol i/o port sink current 5v v ol =0.1v dd 10 20 ? ma i oh i/o port source current 5v v oh =0.9v dd -5 -10 ? ma r ph pull-high resistance 5v ? 10 30 50 kw r ph1 pull-high resistance for data 5v ? ? 4.5 ? kw r ph2 pull-high resistance for clk 5v ? ? 4.5 ? kw i adc additional power consumption if a/d converter is used 5v no load ? 1.5 3.0 ma dnl a/d differential non-linearity ? ? ? ? 2 lsb inl a/d integral non-linearity ? ? 2.5 4.0 lsb resolu resolution ? ? 12 bits ht82a623r/ht82a6208/ht82a6216 rev. 1.30 6 january 14, 2011
a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock ? 2.2v~5.5v ? 6000 ? khz ? 3.0v~5.5v ? 12000 ? khz f timer timer i/p frequency (tmr0/tmr1) ? f sys =6mhz 0 ? 6000 khz f sys =12mhz 0 ? 12000 khz t wdtosc watchdog oscillator period 5v ? ? 65 ? m s t res external reset low pulse width ? ? 1 ? ? ms t sst system start-up timer period ? wake-up from halt ? 1024 ? t sys t opd option load timer period 5v ? 33 70 140 ms t int interrupt pulse width ? ? 1 ? ? m s t ad a/d clock period ? ? 1 ? ? m s t adc a/d conversion time ? ? ? 16 ? t ad t adcs a/d sample time ? ? ? 8 ? t ad t cs_sk spi scsa or scsb to sclka or sclkb time ? ? 50 ? ? ns t spick spi clock time ? ? 166 ? ? ns note: t sys =1/f sys ht82a623r/ht82a6208/ht82a6216 rev. 1.30 7 january 14, 2011
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 8 january 14, 2011 system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to the inter - nal system architecture. the range of devices take ad - vantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it car - ries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the inter - nal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural fea - tures ensure that a minimum of external components is required to provide a functional i/o and a/d control sys - tem with maximum reliability and flexibility. clocking and pipelining the main system clock, derived from a crystal/resona - tor is subdivided into four internally generated non-over - lapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cy - cles, the pipelining structure of the microcontroller en - sures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two instruction cycles are required to com - plete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. f e t c h i n s t . ( p c ) e x e c u t e i n s t . ( p c - 1 ) f e t c h i n s t . ( p c + 1 ) e x e c u t e i n s t . ( p c ) f e t c h i n s t . ( p c + 2 ) e x e c u t e i n s t . ( p c + 1 ) p c p c + 1 p c + 2 o s c i l l a t o r c l o c k ( s y s t e m c l o c k ) p h a s e c l o c k t 1 p r o g r a m c o u n t e r p h a s e c l o c k t 2 p h a s e c l o c k t 3 p h a s e c l o c k t 4 p i p e l i n i n g system clocking and pipelining f e t c h i n s t . 1 e x e c u t e i n s t . 1 f e t c h i n s t . 2 f l u s h p i p e l i n e 1 2 3 4 5 6 d e l a y : m o v a , [ 1 2 h ] c a l l d e l a y c p l [ 1 2 h ] : : n o p e x e c u t e i n s t . 2 f e t c h i n s t . 3 f e t c h i n s t . 6 e x e c u t e i n s t . 6 f e t c h i n s t . 7 instruction fetching
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 9 january 14, 2011 program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as 2jmp2 or 2call2 that demand a jump to a non-consecutive program memory address. it must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable by user. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for condi - tional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is dis - carded and a dummy cycle takes its place while the cor - rect instruction is obtained. the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short pro - gram jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 loca - tions. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. the lower byte of the program counter is fully accessi - ble under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has 6 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, sp, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the con - tents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, sig - naled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. mode program counter bits b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 initial reset 0 0 0 0 0 0 0 0 0 0 0 0 usb interrupt 0 0 0 0 0 0 0 0 0 1 0 0 external interrupt 0 0 0 0 0 0 0 0 1 0 0 0 timer/event counter 0 overflow 0 0 0 0 0 0 0 0 1 1 0 0 spia interrupt 0 0 0 0 0 0 0 1 0 0 0 0 spib interrupt 0 0 0 0 0 0 0 1 0 1 0 0 timer/event counter 1 overflow 0 0 0 0 0 0 0 1 1 0 0 0 skip program counter + 2 loading pcl pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: pc11~pc8: current program counter bits @7~@0: pcl bits #11~#0: instruction code address bits s11~s0: stack register bits p r o g r a m c o u n t e r s t a c k l e v e l 1 s t a c k l e v e l 2 s t a c k l e v e l 3 s t a c k l e v e l 6 p r o g r a m m e m o r y t o p o f s t a c k s t a c k p o i n t e r b o t t o m o f s t a c k
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 10 january 14, 2011 if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac - knowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine in - struction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. arithmetic and logic unit - alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic op - erations of the instruction set. connected to the main microcontroller data bus, the alu receives related in - struction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or oper - ations may result in carry, borrow or other status changes, the status register will be correspondingly up - dated to reflect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti program memory the program memory is the location where the user code or program is stored. the ht82a623r is a one-time programmable, otp, memory type device where users can program their application code into the device. by us - ing the appropriate programming tools, otp devices of - fer users the flexibility to freely develop their applications which may be useful during debug or for products requir - ing frequent upgrades or program changes. otp devices are also applicable for use in applications that require low or medium volume production runs. structure the program memory has a capacity of 4k by 15 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. special vectors within the program memory, certain locations are re - served for special usage such as reset and interrupts. location 000h this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. location 004h this area is reserved for the usb interrupt service program. if the usb interrupt is activated, the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution. location 008h this vector is used by the external interrupt. if the int external input pin on the device receives a high to low transition, the program will jump to this location and begin execution, if the interrupt is enabled and the stack is not full. location 00ch this vector is used by the timer0 counter. if a counter overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. location 010h this vector is used by serial interface a . when 8-bits of data have been received or transmitted success - fully from serial interface a, the program will jump to this location and begin execution if the interrupt is en - abled and the stack is not full. location 014h this vector is used by serial interface b . when 8-bits of data have been received or transmitted success - fully from serial interface a, the program will jump to this location and begin execution if the interrupt is en - abled and the stack is not full f f f h 1 5 b i t s 0 1 4 h i n i t i a l i s a t i o n v e c t o r e x t e r n a l i n t e r r u p t v e c t o r t i m e r / e v e n t c o u n t e r 0 i n t e r r u p t v e c t o r 0 0 0 h 0 0 4 h 0 0 8 h 0 0 c h 0 1 0 h s p i a i n t e r r u p t v e c t o r s p i b i n t e r r u p t v e c t o r 0 1 8 h t i m e r / e v e n t c o u n t e r 1 i n t e r r u p t v e c t o r u s b i n t e r r u p t v e c t o r program memory structure
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 11 january 14, 2011 location 018h this vector is used by the timer1 counter. if a counter overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. look-up table any location within the program memory can be defined as a look-up table where programmers can store fixed data. to use the look-up table, one method is to first setup a low byte table pointer by placing the lower order address of the look up data to be retrieved in the low byte table pointer register, tblp. this register defines the lower 8-bit address of the look-up table. after setting up the table pointer, the table data can be retrieved from the current program memory page or last program memory page using the 2 tabrdc[m] 2 or 2 tabrdl [m]2 instructions, respectively. when these in - structions are executed, the lower order table byte from the program memory will be transferred to the user de - fined data memory register [m] as specified in the in - struction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 202. the following diagram illustrates the addressing/data flow of the look-up table: table program example another method is to setup the full table address using both the tblp and tbhp low and high byte table pointer registers to directly address any area in he program memory. in this way any page of data can be accessed directly using the tabrdl instruction. if the tbhp high byte table pointer register is to be used, then it must first be enabled with a configuration option. the following example shows how the table pointer and table data is defined and retrieved from the microcontroller. this example uses raw table data lo - cated in the last page which is stored there using the org statement. the value at this org statement is 2f00h2 which refers to the start address of the last page within the 4k program memory of device. the table pointer is setup here to have an initial value of 206h2. this will ensure that the first data read from the data ta - ble will be at the program memory address 2f06h2 or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the first ad- dress of the present page if the 2 tabrdc [m]2 instruc- tion is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the 2 tabrdl [m]2 in - struction is executed. instruction table location bits b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m] pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: pc11~pc8: current program counter bits tbhp register bit3~bit0 when tbhp is enabled @7~@0: table pointer tblp bits p r o g r a m m e m o r y p r o g r a m c o u n t e r h i g h b y t e t b l p t b l h s p e c i f i e d b y [ m ] t a b l e c o n t e n t s h i g h b y t e t a b l e c o n t e n t s l o w b y t e table read - tblp only p r o g r a m m e m o r y t b l h s p e c i f i e d b y [ m ] h i g h b y t e o f t a b l e c o n t e n t s l o w b y t e o f t a b l e c o n t e n t s t b l p t b h p table read - tblp/tbhp
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 12 january 14, 2011 table program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer - note that this address ; is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempregl ; data at prog. memory address 2f06h2 transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog.memory address 2f05h2 transferred to ; tempreg2 and tblh ; in this example the data 21ah2 is transferred to ; tempreg1 and data 20fh2 to register tempreg2 ; the value 200h2 will be transferred to the high byte ; register tblh : : org f00h ; sets initial address of last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 13 january 14, 2011 because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use the table read instructions. if using the table read instructions, the interrupt service routines may change the value of tblh and subsequently cause er - rors if used again by the main routine. as a rule it is rec - ommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the inter - rupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary in - formation is stored. divided into two sections, the first of these is an area of ram where special function registers are located. these registers have fixed locations and are necessary for correct operation of the device. many of these registers can be read from and written to di - rectly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. structure the two sections of data memory, the special purpose and general purpose data memory are located at con- secutive locations. all are implemented in ram and are 8 bits wide but the length of each memory section is dic- tated by the type of microcontroller chosen. the start address of the data memory for all devices is the ad - dress 2 00h 2 . registers which are common to all microcontrollers, such as acc, pcl, etc., have the same data memory address. general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user pro - gram for both read and write operations. by using the 2 set [m].i2 and 2 clr [m].i2 instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the data memory. 0 0 h 6 0 h f f h 5 f h s p e c i a l p u r p o s e d a t a m e m o r y g e n e r a l p u r p o s e d a t a m e m o r y data memory structure note: most of the data memory bits can be directly manipulated using the 2 set [m].i2 and 2clr [m].i2 with the exception of a few dedicated bits. the data memory can also be accessed through the memory pointer register mp. 0 0 h 0 1 h 0 2 h 0 3 h 0 4 h 0 5 h 0 6 h 0 7 h 0 8 h 0 9 h 0 a h 0 b h 0 c h 0 d h 0 e h 0 f h 1 0 h 1 1 h 1 2 h 1 3 h 1 4 h 1 5 h 1 6 h 1 7 h 1 8 h 1 9 h 1 a h 1 b h 1 c h 1 d h 1 e h 1 f h 2 0 h 2 1 h 2 2 h 2 3 h 2 4 h 2 5 h 2 6 h 2 7 h 2 8 h 2 9 h 2 a h 2 b h 2 c h 2 d h : u n u s e d r e a d a s " 0 0 " i a r 0 m p 0 i a r 1 m p 1 a c c p c l t b l p t b l h w d t s s t a t u s i n t c 0 t m r 1 h t m r 1 l t m r 1 c t m r 0 h t m r 0 l t m r 0 c p a p a c p b p b c p c p c c p d p d c u s b _ s t a t u i n t i n t c 1 t b h p u s c u s r u c c a w r s t a l l s i e s m i s c u f i e n f i f o 0 f i f o 1 f i f o 2 f i f o 3 2 e h 2 f h 3 0 h 3 1 h 3 2 h 3 3 h 3 4 h 3 5 h 3 6 h 3 7 h 3 8 h 3 9 a 3 a h 3 b h 3 c h 3 d h 3 e h 3 f h 4 0 h 4 1 h 4 2 h 4 3 h 4 4 h 4 5 h 4 6 h 4 7 h 4 8 h 4 9 h 4 a h 4 b h 4 c h 4 d h 4 e h 4 f h 5 0 h 5 1 h 5 2 h 5 3 h 5 4 h 5 5 h 5 6 h 5 7 h 5 8 h 5 9 h 5 a h u f o e n u f c 0 s b c r a s b d r a a d r l a d r h a d c r a c s r s b c r b s b d r b m o d e s p i _ r e g p w m b r 0 p w m 0 d r p w m b r 1 p w m 1 d r p w n c t l
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 14 january 14, 2011 special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writable but some are protected and are readable only, the details of which are located under the relevant spe - cial function register section. note that for locations that are unused, any read instruction to these addresses will return the value 200h2. special function registers to ensure successful operation of the microcontroller, certain internal registers are implemented in the data memory area. these registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as i/o data control. the location of these registers within the data memory be - gins at the address 00h. any unused data memory lo - cations between these special function registers and the point where the general purpose memory begins is re - served and attempting to read data from these locations will return a value of 00h. indirect addressing register - iar0, iar1 the iar0 and iar1 register, although having their loca - tions in normal ram register space, do not actually physically exist as normal registers. the method of indi - rect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specified. actions on the iar0 and iar1 registers will result in no actual read or write opera - tion to these registers but rather to the memory location specified by their corresponding memory pointer, mp0 or mp1. acting as a pair, iar0 and mp0 can together only access data from bank 0, while the iar1 and mp1 register pair can access data from both bank 0 and bank 1. as the indirect addressing registers are not physically implemented, reading the indirect ad - dressing registers indirectly will return a result of 200h2 and writing to the registers indirectly will result in no op - eration. memory pointer - mp0, mp1 for all devices, two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers pro - viding a convenient way with which to address and track data. when any operation to the relevant indirect ad - dressing registers is carried out, the actual address that the microcontroller is directed to, is the address speci - fied by the related memory pointer. data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1; accumulator loaded with first ram address mov mp0,a ; setup memory pointer with first ram address loop: clr iar0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific data memory ad - dresses.
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 15 january 14, 2011 accumulator - acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register - pcl to provide additional program control functions, the low byte of the program counter is made accessible to pro - grammers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily imple - mented. loading a value directly into this pcl register will cause a jump to the specified program memory lo - cation, however, as the register is only 8-bit wide, only jumps within the current program memory page are per - mitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers - tblp, tbhp, tblh these three special function registers are used to con- trol operation of the look-up table which is stored in the program memory. tblp and tbhp are the table pointer low and high byte registers and indicate the location where the table data is located. there value must be setup before any table read commands are executed. their value can be changed, for example using the 2inc2 or 2dec2 instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user de - fined location. status register - status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system manage - ment flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera - tions related to the status register may give different re - sults due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the 2 clr wdt2 or 2 halt2 in - struction. the pdf flag is affected only by executing the 2 halt2 or 2 clr wdt2 instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. c is set if an operation results in a carry during an ad - dition operation or if a borrow does not take place dur - ing a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nib - ble into the low nibble in subtraction; otherwise ac is cleared. z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov is set if an operation results in a carry into the high- est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pdf is cleared by a system power-up or executing the 2 clr wdt2 instruction. pdf is set by executing the 2halt2 instruction. to is cleared by a system power-up or executing the 2 clr wdt2 or 2halt2 instruction. to is set by a wdt time-out. t o p d f o v z a c c s t a t u s r e g i s t e r a r i t h m e t i c / l o g i c o p e r a t i o n f l a g s c a r r y f l a g a u x i l i a r y c a r r y f l a g z e r o f l a g o v e r f l o w f l a g s y s t e m m a n a g e m e n t f l a g s p o w e r d o w n f l a g w a t c h d o g t i m e - o u t f l a g n o t i m p l e m e n t e d , r e a d a s " 0 " b 7 b 0 status register
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 16 january 14, 2011 in addition, on entering an interrupt sequence or execut - ing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the interrupt rou - tine can change the status register, precautions must be taken to correctly save it. interrupt control registers - intc0, intc1 the microcontrollers provide one external interrupt, two internal timer/event counter overflow interrupts, two spi interrupts and one usb interrupt. by setting various bits within these registers using standard bit manipulation instructions, the enable/disable function of each inter - rupt can be independently controlled. a master interrupt bit within this register, the emi bit, acts like a global en - able/disable and is used to set all of the interrupt enable bits on or off. this bit is cleared when an interrupt routine is entered to disable further interrupt and is set by exe - cuting the 2 reti 2 instruction. timer/event counter registers - tmr0h/tmr1h, tmr0l/tmr1l,tmr0c/tmr1c all devices possess two internal 16-bit count-up timer. an associated register pair known as tmr0l/tmr0h and tmr1l/tmr1h are the locations where the timer 16-bit values are located. these registers can also be preloaded with fixed data to allow different time intervals to be setup. associated control registers, known as tmr0c and tmr1c, contains the setup information for the timers, which determines in what mode the timer is to be used as well as containing the timer on/off control function. input/output ports and control registers within the area of special function registers, the i/o registers and their associated control registers play a prominent role. all i/o ports have a designated register correspondingly labeled as pa, pb, pc and pd. these labeled i/o registers are mapped to specific addresses within the data memory as shown in the data memory table, which are used to transfer the appropriate output or input data on that port. with each i/o port there is an associated control register labeled pac, pbc, pcc and pdc, also mapped to specific addresses with the data memory. the control register specifies which pins of that port are set as inputs and which are set as outputs. to setup a pin as an input, the corresponding bit of the con - trol register must be set high, for an output it must be set low. during program initialisation, it is important to first setup the control registers to specify which pins are out - puts and which are inputs before reading data from or writing data to the i/o ports. one flexible feature of these registers is the ability to directly program single bits us - ing the 2 set [m].i2 and 2 clr [m].i2 instructions. the ability to change i/o pins from output to input and vice versa by manipulating specific bits of the i/o control reg - isters during normal program operation is a useful fea - ture of these devices. flash memory the ht82a6208 contains a 8,388,608 bit serial flash memory, which has an internal configuration of 1,048,576 8. the ht82a6208 internal flash memory contains a 16,777,216 bit serial flash memory, with a 2,097,152 8 internal configuration. the ht82a623r does not contain flash memory. device size configuration ht82a623r ? ? ht82a6208 8m 1,048,5768 ht82a6216 16m 2,097,1528 flash memory description the ht82a6208/ht82a6216 internal flash memory feature a serial peripheral interface and software proto - col which permits operation using a simple 3-wire bus. the three bus signals are a clock input, fhsclk, serial data input, fhsi, and serial data output, fhso. the spi access to the device is enabled using the fhcs# input. there is a sequential read operation for the whole de - vice. after a program/erase command is issued, the auto pro- gram/erase algorithms which program/erase and verify the specified page or byte/sector/block locations will be executed. program command is executed on a page, 256 byte, basis, and an erase command is executed on chip or sector, 4k-bytes, or block, 64k-bytes. to provide the user with a simplistic interface, a status register is in - cluded to indicate the status of the device. the status read command can be issued to detect a completion status of a program or erase operation using the wip bit. when the ht82a6208/ht82a6216 internal flash mem - ory is not in operation and fhcs# is high, the device will be place into a standby mode where it will draw less than 10 m a/20 m a dc current. the ht82a6208/ht82a6216 in - ternal flash memory reliably stores its memory contents even after 100,000 program and erase cycles. data protection the device is designed to offer protection against acci - dental erasure or programming caused by spurious sys - tem level signals that may exist during power transition. during power up the device automatically resets the state instruction in the read mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of spe - cific command sequences. the device also incorpo -
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 17 january 14, 2011 rates several features to prevent inadvertent write cycles during power-on and power-down transitions or due to system noise. these features are: power-on reset and t puw : to avoid problems due to sys - t em power supply transitions, the power-on reset and t puw (internal timer) may protect the flash memory. v alid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. write enable (wren) command: the wren com - mand is required to set the write enable latch bit (wel) before other commands to change data. the wel bit will return to its reset condition under the fol - lowing situations: power-on write disable (wrdi) command completion write status register (wrsr) command completion page program (pp) command completion continuous program mode (cp) instruction completion - only for ht82a6216 internal flash memory sector erase (se) command completion block erase (be) command completion chip erase (ce) command completion write read-lock bit (wrlb) instruction completion - only for ht82a6216 internal flash memory deep power down mode: by entering the deep power down mode, the flash memory is also under protection from all write commands except for the release from deep power down mode command (rdp) and read electronic signature command (res ). software protection mode (spm): by using the bp register bits bp0~bp3, sections of the flash memory can be protected. hardware protection mode (hpm): keeping wp low will protect the bp0~bp3 bits and the srwd bit from a state change. status bit protect level 8mb bp2 bp1 bp0 0 0 0 0 (none) none 0 0 1 1 (1 block) block 15 0 1 0 2 (2 blocks) block 14~15 0 1 1 3 (4 blocks) block 12~15 status bit protect level 8mb bp2 bp1 bp0 1 0 0 4 (8 blocks) block 8~15 1 0 1 5 (all) all 1 1 0 6 (all) all 1 1 1 7 (all) all protected flash area - ht82a6208 status bit 16mb bp3 bp2 bp1 bp0 0 0 0 0 0 (none) 0 0 0 1 1 (1block, block 31th) 0 0 1 0 2 (2blocks, block 30~31th) 0 0 1 1 3 (4blocks, block 28~31th) 0 1 0 0 4 (8blocks, block 24~31th) 0 1 0 1 5 (16blocks, block 16~31th) 0 1 1 0 6 (32blocks, all) 0 1 1 1 7 (32blocks, all) 1 0 0 0 8 (32blocks, all) 1 0 0 1 9 (32blocks, all) 1 0 1 0 10 (16blocks, block 0~15th) 1 0 1 1 11 (24blocks, block 0~23th) 1 1 0 0 12 (28blocks, block 0~27th) 1 1 0 1 13 (30blocks, block 0~29th) 1 1 1 0 14 (31blocks, block 0~30th) 1 1 1 1 15 (32blocks, all) protected flash area - ht82a6216 hold features the fhhold pin signal goes low to hold any serial communications with the device. the hold features will not stop the function of the write status register or any programming erase operation in progress. the hold operation requires that the chip select, (fhcs#) is kept low and starts on the falling edge of the fhhold pin signal while the serial clock (fhsclk) signal is low (if serial clock signal is not being low. the hold operation will not start until the serial clock is low). the hold condition ends on the rising edge of the fhhold pin signal white the serial clock (fhsclk) figure 1. hold condition operation fhsclk fhcs# fhhold
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 18 january 14, 2011 signal is low. if the serial clock signal is low, the hold operation will not end until the serial clock being is low for the following figure 1. the serial data output (fhso) is high impedance, both serial data input (fhsi) and serial clock (fhsclk) are don t care during the hold operation. if the chip select (fhcs#) is set high during the hold operation then it will reset the internal logic of the device. to re-start com - munication with the device, the fhhold pin must be high and fhcs# must be low. for the ht82a6208/ht82a6216, the internal flash memory fhhold pin must is bound to the vcc pin. memory organisation the internal memory blocks of the flash memory includ - ing the sector and address range is shown in the follow - ing tables. table 1. flash memory organisation - ht82a6208
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 19 january 14, 2011 table 2. 16mb flah memory organisation - ht82a6216 table 2. 16mb flash memory organisation - ht82a6216
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 20 january 14, 2011 command definitions the internal flash memory operates using a range of commands issued serially by the microcontroller to the flash memory. these commands are summarised in the accompanying table. flash memory command definition - ht82a6208 fhcs# goes high
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 21 january 14, 2011 flash memory command definition - ht82a6216 fhcs# fhcs# fhcs#
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 22 january 14, 2011 flash memory operation the following statements show the basic protocol be - hind each flash memory command execution. before a command is issued, the status register should be checked to ensure that the device is ready for the intended operation. when a correct command is input to the device, it will enter the standby mode and remain in the standby mode until the next fhcs# falling edge. in the standby mode, the device fhso pin should be high-z. when a correct command is input to the device, it will enter the active mode and remain in the active mode until the next fhcs# rising edge. the input data is latched on the rising edge of the se - rial clock, fhsclk, and the data is shifted out on the falling edge of fhsclk. the difference between spi mode 0 and mode 3 is shown in figure 2. for the following instructions: rdid, rdsr, read, fast_read, res and rems the shifted-in instruc - tion sequence is followed by a data-out sequence. af - ter any data bit is shifted out, fscs# can be high. for the following instructions: wren, wrdi, wrsr, se, be, ce, pp, rdp and dp, cs must go high exactly at the byte boundary; otherwise the instruction will be re - jected and not executed. during the progress of write status register, pro - gram, erase operations, the memory array access is neglected and therefore does not affect the current operation of the write status register, program, erase. command description the following provides a detailed description of each flash memory command. write enable - wren the write enable, wren, instruction is used to set the write enable latch, wel, bit. for instructions like pp, se, be, ce, and wrsr, which are intended to change the device contents, it should be set every time after the wren instruction sets the wel bit. the sequence to execute the wren instruction is: fhcs# goes low ? send wren instruction code ? fhcs# goes high. write disable - wrdi the write disable, wrdi, instruction is for resetting the write enable latch, wel, bit. the sequence of is - suing the wrdi instruction is: fhcs# goes low ? send wrdi instruction code ? fhcs# goes high. the wel bit is reset by following conditions: power-up write disable, wrdi, instruction completion write status register (wrsr) instruction completion page program (pp) instruction completion sector erase (se) instruction completion block erase (be) instruction completion chip erase (ce) instruction completion note: cpol indicates clock polarity of the spi master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of the cpol bit and cpha bit decides which spi mode is supported. figure 2. supported spi modes write enable (wren) sequence (command 06) write disable (wrdi) sequence (command 04) fhcs# fhsclk fhsi fhso fhso fhsi fhsclk fhcs# fhsi fhso fhsclk fhsclk
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 23 january 14, 2011 read identification - rdid the rdid instruction is for reading the manufacturer 1-byte id followed by the 2-byte device id. the device manufacturer id is c2(hex), the memory type id is 20(hex) as the first-byte device id, and the individual device id of second-byte id is as follows: 14(hex) for the ht82a6208/ht82a6216 internal flash memory. the sequence for issuing the rdid instruction is: fhcs# goes low ? sending rdid instruction code ? 24-bits id data out on so ? to end rdid operation can use fhcs# high at any time during data out. while the program/erase operation is in progress, it will not decode the rdid instruction, so there is no ef - fect on the cycle of program/erase operation which is currently in progress. when fhcs# goes high, the de - vice is in the standby stage. read status register - rdsr the instruction is for reading the status register bits. the read status register can be read at any time (even in the program/erase/write status register con - dition) and continuously. it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status reg - ister operation is in progress. the sequence to issue the rdsr instruction is: fhcs# goes low ? sending rdsr instruction code ? status register data out on so. the definition of the status register bits is shown be - low: wip bit the write in progress (wip) bit, a volatile bit, indi - cates whether the device is busy in pro - gram/erase/write status register progress. when the wip bit is set to 212 , this means the device is busy in program/erase/write status register prog - ress. when the wip bit is set to 202 , this means the device is not in progress of program/erase/write sta - tus register cycle. wel bit the write enable latch (wel) bit, a volatile bit, indi - cates whether the device is set to internal write en - able latch. when the wel bit is set to 212 , which means the internal write enable latch is set, the de - vice can accept program/erase/write status register instructions. when the wel bit is cleared to 202, which means no internal write enable latch; the de - vice will not accept program/erase/write status reg - ister instructions. bp0~bp3 bits the block protect bits bp0~bp3, are non-volatile bits, which indicate the protected area (as defined in the table) of the device against the program/erase instruction without the hardware protection mode being set. to write the block protect bits requires the write status register (wrsr) instruction to be executed. those bits define the protected area of read identification (rdid) sequence (command 9f) read status register (rdsr) sequence (command 05) fhcs# fhsclk fhsi fhso fhso fhsi fhsclk fhcs#
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 24 january 14, 2011 the memory against page program (pp), sector erase (se), block erase (be) and chip erase(ce) instructions (only if all block protect bits are set to 202, can the ce instruction be executed). srwd bit t he status register write disable (srwd) bit, non-volatile bit, is operated together with the write protection (fhwp ) pin to provide the hardware pro - tection mode. the hardware protection mode re - quires that srwd is set to 212 and the wp# pin signal is low . in the hardware protection mode, the write status register (wrsr) instruction is no lon - ger accepted for execution and the srwd bit and block protect bits (bp0~bp3) are read only. for the ht82a6208/ht82a6216 internal flash memory, the write protection (fhwp ) pin is always bonded with the gnd pin write status register - wrsr the wrsr instruction is used to change the values of the status register bits. before sending an wrsr in - struction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in advance. the wrsr instruction can change the value of the block protect (bp0~bp3) bits to define the protected area of memory (as shown in the table). the wrsr also can set or reset the sta - tus register write disable (srwd) bit in accordance with the write protection (wp#) pin signal. the wrsr instruction cannot be executed once the hardware protected mode is entered. the sequence to issue wrsr instruction is: fhcs# goes low ? sending wrsr instruction code ? status register data on si ? fhcs# goes high. (see figure 3). the wrsr instruction has no effect on b6, b5, b1, b0 of the status register. figure 3. write status register (wrsr) sequence (command 01) note: 1. see the table 2protected flash area 2. 2. the endurance cycles for the protect bits are 100,000 cycles; however, the tw time out spec for the protect bits is relaxed to t w = n 15ms (n is a multiple of 10,000 cycles, ex. n = 2 for 20,000 cycles) after 10,000 cycles on those bits. status register - ht82a6208 internal flash memory note: see the table 2protected flash area 2 status register - ht82a6216 internal flash memory fhcs# fhsclk fhsi fhso
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 25 january 14, 2011 note: as defined by the values in the block protect (bp2, bp1, bp0) bits of the status register, as shown in table 1. the above table shows the summary of the software protected mode, spm, and hardware protected mode, hpm. software protected mode - spm: when the srwd bit=0, no matter if fhwp is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp2, bp1, bp0. the protected area, which is defined by bits bp2, bp1, bp0, is in the software protected mode. when the srwd bit=1 and fhwp is high, the wren instruction may set the wel bit and can change the values of srwd, bp2, bp1, bp0. the protected area, which is defined by bp2, bp1, bp0, is in the software protected mode. note: if srwd bit=1 but fhwp is low, it is impossible to write to the status register even if the wel bit has previously been set. hardware protected mode - hpm: when the srwd bit=1, and then fhwp is low (or fhwp is low before srwd bit=1), the device enters the hardware protected mode. the protected area data, defined by bits bp2, bp1, bp0 and hardware protected mode using fhwp is protected against data modification. note: to exit the hardware protected mode requires that fhwp is set high once the hardware protected mode is entered. if the fhwp pin is permanently connected high, the hardware protected mode can never be en- tered; only software can be used to enter the protected mode via bits bp2, bp1, bp0. protection modes - ht82a6208 internal flash memory fhwp fhwp fhwp fhwp fhwp
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 26 january 14, 2011 note: as defined by the values in the block protect (bp3, bp2, bp1, bp0) bits of the status register, as shown in table 1. the above table shows the summary of the software protected mode (spm) and hardware protected mode (hpm). software protected mode - spm: when the srwd bit=0, no matter if fhwp /acc is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defined by bp3, bp2, bp1, bp0, is in the software protected mode (spm). when the srwd bit=1 and fhwp /acc is high, the wren instruction may set the wel bit and can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defined by bp3, bp2, bp1, bp0, is in the software protected mode (spm) note: if the srwd bit=1 but fhwp /acc is low, it is impossible to write to the status register even if the wel bit has previously been set. it is rejected to write to the status register and not be executed. hardware protected mode - hpm: when the srwd bit=1, and then fhwp /acc is low (or fhwp /acc is low before srwd bit=1), it enters the hardware protected mode. the data of the protected area is protected by the software protected mode by bp3, bp2, bp1, bp0 and the hardware protected mode by the fhwp /acc against data modification. note: to exit the hardware protected mode requires fhwp /acc is driven high once the hardware protected mode is entered. if the fhwp /acc pin is permanently connected high, the hardware protected mode can never be entered; only the software protected mode can be used via bp3, bp2, bp1, bp0. protection modes - ht82a6216 internal flash memory fhwp fhwp fhwp fhwp fhwp
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 27 january 14, 2011 cs must go high exactly at the byte boundary; other - wise, the instruction will be rejected and not executed. the self-timed write status register cycle time (t w ) is initiated as soon as the chip select (fhcs#) goes high. the write in progress (wip) bit can still be checked when the write status register cycle is in progress. the wip is set to 212 during the t w timing, and cleared 202 when the write status register cycle has completed, and the write enable latch (wel) bit is reset. read data bytes - read the read instruction is for reading data out. the ad - dress is latched on the rising edge of fhsclk, and data shifts out on the falling edge of fhsclk at a maximum frequency f r . the first address byte can be a t any location. the address is automatically in - creased to the next higher address after each data byte is shifted out, so the whole memory can be read out with a single read instruction. the address coun - ter rolls over to 202 when the highest address has been reached. the sequence to issue a read instruction is: fhcs# goes low ? sending read instruction code ? 3-byte address on si ? data out on so ? to end a read operation, fhcs# going high can be used at any time during data out. read data bytes at higher speed - fast_read the fast_read instruction is to read data out quickly. the address is latched on the rising edge of sclk, and each bit of data is shifted out on the falling edge of sclk at a maximum frequency f c . the first address byte can be at any location. the address is automatically increased to the next higher address af - ter each data byte is shifted out, so the whole memory read data bytes (read) sequence (command 03) figure 4. read at higher speed (fast_read) sequence (command 0b) fhcs# fhsclk fhsi fhso fhcs# fhsclk fhsi fhso fhcs# fhsclk fhsi fhso
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 28 january 14, 2011 can be read out with a single fast_read instruction. the address counter rolls over to 202 when the highest address has been reached. the sequence to issue a fast_read instruction is: fhcs# goes low ? sending fast_read instruction code ? 3-byte address on si ? 1-dummy byte ad - dress on si ? data out on so ? to end fast_read operation can use fhcs# going high at any time dur - i n g d a t a o u t . ( s e e f i g u r e 4 ) w h i l e p r o - gram/erase/write status register cycle is in progress, fast_read instruction is rejected without any impact on the program/erase/write status regis - ter current cycle. sector erase - se the sector erase (se) instruction is used to erase the data of the chosen sector to 212 . a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the sector erase (se). any address in the sector (see table 1 or table 2) is a valid address for a sector erase (se) in - struction. cs must go high exactly at the byte bound - ary (when the latest eighth address byte has been latched-in); otherwise, the instruction will be rejected and not executed. address bits [am-a12] (am is the most significant ad - dress) select the sector address. the sequence to is - sue a se instruction is: fhcs# goes low ? sending se instruction code ? 3-byte address on si ? fhcs# goes high. the self-timed sector erase cycle time (tse) is initi- ated as soon as the chip select (cs) goes high. the write in progress (wip) bit can still be checked when a sector erase cycle is in progress. wip is set to 212 during the tse timing, and cleared to 202 when the sector erase cycle is completed, and the write en - able latch (wel) bit is reset. if the page is protected by bp2, bp1, bp0 or bp3, bp2, bp1, bp0 bitts, the sector erase (se) instruction will not be executed on the page. block erase - be the block erase (be) instruction erases data of the chosen block to 212 . a write enable (wren) instruc - tion must executed to set the write enable latch (wel) bit before sending the block erase (be). any addresses of the block (see table 1 or table 2) are valid addressed for a block erase (be) instruction. cs must go high exactly at the byte boundary (when the latest eighth address byte been latched-in); other - wise, the instruction will be rejected and not executed. the sequence of issuing be instruction is: fhcs# goes low ? sending be instruction code ? 3-byte ad - dress on si ? fhcs# goes high. the self-timed block erase cycle time (tbe) is initi - ated as soon as chip select (fhcs#) goes high. the write in progress (wip) bit still can be checked out when the sector erase cycle is in progress. the wip is set to 212 during the tbe timing, and cleared to 202 when the sector erase cycle has completed, and the write enable latch (wel) bit is reset. if the page is protected by bp0~bp3 bits, the block erase (be) in - struction will not be executed on the page. note: se command is 20(hex). sector erase (se) sequence (command 20) note: be command is 52 or d8(hex). block erase (be) sequence (command 52 or d8) fhcs# fhsclk fhsi fhsi fhsclk fhcs#
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 29 january 14, 2011 chip erase - ce the chip erase (ce) instruction is used to erase the data of the whole chip to 212 . a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the chip erase (ce). any address of the sector (see table 1 or table 2) is a valid address for the chip erase (ce) instruction. fhcs# must go high exactly at the byte boundary (when the latest eighth address byte has been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing ce instruction is: fhcs# goes low ? sending ce instruction code ? fhcs# goes high. (see figure 5). the self-timed chip erase cycle time (tce) is initiated as soon as the chip select (fhcs#) goes high. the write in progress (wip) bit still can be checked when the chip erase cycle is in progress. the wip is set to 212 during the tce timing, and cleared to 202 when the chip erase cycle has completed, and the write en - able latch (wel) bit is reset. if the chip is protected by the bp0~bp3 bits, the chip erase (ce) instruction will not be executed. it will be only executed when bp0~bp3 are all set to 202. page program - pp the page program (pp) instruction is used to pro - gramming the memory to 202 . a write enable (wren) instruction must executed to set the write enable latch (wel) bit before sending the page program (pp). if the eighth least significant address bits (a7~a0) are not all 0, all transmitted data which goes beyond the end of the current page are programmed from the start address if the same page (from the ad - dress whose 8 least significant address bits (a7~a0) are all 0). fhcs# must go high exactly at the byte boundary (when the latest eighth address byte been latched-in); otherwise, the instruction will be rejected and not executed. if more than 256 bytes are sent to the device, the data of the last 256-bytes are pro - grammed at the request page and previous data will be disregarded. if less than 256 bytes are sent to the device, the data is programmed at the request ad - dress of the page without effect on other address of the same page. note: ce command is 60(hex) or c7(hex). figure 5. chip erase (ce) sequence (command 60 or c7) figure 6. page program (pp) sequence (command 02) fhcs# fhsclk fhsi fhcs# fhsclk fhsi fhcs# fhsclk fhsi
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 30 january 14, 2011 release from deep power-down and read electronic signature (res) sequence (command ab) figure 7. deep power-down (dp) sequence (command b9) the sequence to issue a pp instruction is: fhcs# goes low ? sending pp instruction code ? 3-byte ad - dress on si ? at least 1-byte on data on si ? fhcs# goes high (see figure 6). the self-timed page program cycle time(tpp) is initi - ated as soon as the chip select (fhcs#) goes high. the write in progress (wip) bit still can still be checked when the page program cycle is in progress. wip is set to 212 during the tpp timing, and cleared to 202 when the page program cycle has completed, and the write enable latch (wel) bit is reset. if the page is protected by the bp0~bp3 bits, the page pro - gram (pp) instruction will not be executed. deep power-down - dp the deep power-down (dp) instruction is used to set the device to a condition of minimum power consump - tion. the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to be executed. during the deep power-down mode, the device is not active and all write/ program/erase instructions are ignored. when fhcs# goes high, it will only be in standby mode and not in deep power-down mode. the sequence to issue a dp instruction is: fhcs# goes low ? sending dp instruction code ? fhcs# goes high. (see figure 7) once the dp instruction is executed, all instructions will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res ) instruction. (res in - struction to allow the id been read out). during power-down, the deep power-down mode automati - cally stops, and when powered-up, the device auto - matically is in standby mode. for the rdp instruction fhcs# must go high exactly at the byte boundary (when the latest eighth bit of the instruction code has been latched-in); otherwise, the instruction will not be executed. as soon as the chip select (fhcs#) goes high, a delay of tdp is required before entering the deep power-down mode and reducing the current to isb2. release from deep power-down (rdp), read elec - tronic signature (res) the release from deep power-down (rdp) instruc - tion is terminated by driving chip select (fhcs#) high. when chip select (fhcs#) is driven high, the device is put into the stand-by power mode. if the de - vice was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by tres2, and chip select (fhcs#) must remain high for at least tres2(max), as specified in the table. once in the stand-by power mode, the device waits to be se - lected, so that it can receive, decode and execute in - structions. the res instruction reads out the old style of 8-bit electronic signature, whose values are shown in the table of id definitions. this is not the same as the rdid instruction. it is not recommended to use fhcs# fhsclk fhsi fhcs# fhsclk fhsi fhso
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 31 january 14, 2011 this for new designs. for new designs, use the rdid instruction. even in deep power-down mode, the rdp and res are also allowed to be executed, except when the device is in the program/erase/write cycle; here there is no effect on the current pro - gram/erase/write cycle in progress. the sequence is shown as figure 8. the res instruction is ended when fhcs# goes high after the id has been read out at least once. the id outputs repeatedly if additional clock cycles on fhsclk are repeatedly sent while fhcs# is low. if the device was not previously in the deep power-down mode, the device transition to standby mode is immediate. if the device was previously in the deep power-down mode, there is a delay of tres2 to transition to the standby mode, and fhcs# must re- main high for at least tres2(max). once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. the rdp instruction is to release the device from the deep power-down mode. read electronic manufacturer id & device id (rems) - for the ht82a6208 internal flash memory the rems instruction is an alternative to the release from power-down/device id instruction that provides both the jedec assigned manufacturer id and the specific device id. the rems instruction is very similar to the release from power-down/device id instruction. the instruc - tion is initiated by driving the fhcs# pin low and shifting the instruction code 290h2 followed by two dummy bytes and one bytes address (a7~a0). after this, the manufacturer id for the device (c2h) and the device id are shifted out on the falling edge of fhsclk with the most significant bit (msb) first as shown in figure 9. the device id values are listed in the id definition table. if the one-byte address is ini - tially set to 01h, then the device id will be read first and then followed by the manufacturer id. the manu - facturer and device ids can be read continuously, al - ternating from one to the other. the instruction is completed by driving fhcs# high. command type ht82a6208 internal flash memory rdid manufacture id memory type memory density c2 20 14 res electronic id 13 rems manufacture id device id c2 13 figure 8. release from deep power-down (rdp) sequence (command ab) fhcs# fhsclk fhsi fhso
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 32 january 14, 2011 notes: add=00h will output the manufacturer's id first and add=01h will output device id first figure 9. read electronic manufacturer & device id (rems) sequence (command 90) fhcs# fhsclk fhsi fhso fhcs# fhsclk fhsi fhso
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 33 january 14, 2011 notes: add=00h will output the manufacturer's id first and add=01h will output device id first figure 10. read electronic manufacturer & device id (rems) sequence (command 90) read electronic manufacturer id & device id (rems), (rems2) - ht82a6216 internal flash memory the rems & rems2 instruction is an alternative to the release from power-down/device id instruction that provides both the jedec assigned manufacturer id and the specific device id. the rems & rems2 instruction is very similar to the release from power-down/device id instruction. the instruction is initiated by driving the fhcs# pin low and shifting the instruction code 290h2 or 2efh2 fol - lowed by two dummy bytes and one bytes address (a7~a0). after this, the manufacturer id for mxic (c2h) and the device id are shifted out on the falling edge of fhsclk with most significant bit (msb) first as shown in figure 10. the device id values are listed in table of id definitions. if the one-byte address is ini - tially set to 01h, then the device id will be read first and then followed by the manufacturer id. the manu - facturer and device ids can be read continuously, al - ternating from one to the other. the instruction is completed by driving fhcs# high. command type ht82a6216 internal flash memory rdid (jedec id) manufacture id memory type memory density c2 20 15 res electronic id 14 rems/rems2 manufacture id device id c2 14 fhcs# fhsclk fhsi fhso fhcs# fhsclk fhsi fhso
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 34 january 14, 2011 fhcs# =vcc fhsclk fhcs# =vcc fhsclk fhsclk fhcs# =vcc fhcs# =vcc fhcs# =vcc fhcs# =vcc
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 35 january 14, 2011 figure 11. maximum negative overshoot waveform fhcs# active setup time (relative to fhsclk) fhcs# not active hold time (relative to fhsclk) fhcs# active hold time (relative to fhsclk) fhcs# not active setup time (relative to fhsclk) fhcs# deselect time fhhold setup time (relative to fhsclk) fhhold hold time (relative to fhsclk) fhhold hold time (relative to fhsclk) fhhold setup time (relative to fhsclk) fhhold to output low-z fhhold to output high-z fhcs# high to deep power-down mode fhcs# high to standby mode without electronic signature read fhcs# high to standby mode with electronic signature read
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 36 january 14, 2011 serial input timing output timing hold timing fhcs# fhsclk fhsi fhso fhcs# fhsclk fhso fhsi fhcs# fhsclk fhhold fhso
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 37 january 14, 2011 power-up timing fhwp disable setup and hold timing during wrsr when srwd=1 fhcs# fhsclk fhsi fhso fhwp
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 38 january 14, 2011 ht82a6208 internal flash memory ht82a6216 internal flash memory figure 12. ac timing at device power-up recommended operating conditions at device power-up ac timing illustrated in figure 12 is recommended for the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly.
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 39 january 14, 2011 ht82a6208 internal flash memory erase and programming performance ht82a6216 internal flash memory
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 40 january 14, 2011 input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. with the input or output designation of ev - ery pin fully under user program control, pull-high op - tions for all ports and wake-up options on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. depending upon which package is chosen, the microcontroller provides up to 32 bidirectional input/out - put lines labeled with port names pa, pb, pc and pd. these registers are mapped to the data memory with an addresses as shown in the special purpose data mem - ory table. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction 2 mov a,[m]2 , where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an exter - nal resistor. to eliminate the need for these external re - sistors, i/o pins, when configured as an input have the capability of being connected to an internal pull-high re - sistor. the pull-high resistors are selectable via configu - ration options and are implemented using weak pmos transistors. pa pins have bit select pull-high configura - tion options. other ports have nibble select pull-high configuration options. port pin wake-up if the halt instruction is executed, the device will enter the power down mode, where the system clock will stop resulting in power being conserved, a feature that is im - portant for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port pins from high to low. after a halt instruction forces the microcontroller into entering the power down mode, the processor will remain in a low-power state un - til the logic condition of the selected wake-up pin on the port pin changes from high to low. this function is espe - cially suitable for applications that can be woken up via external switches. pa pins have bit select wake-up configuration options. other ports have nibble select wake-up configuration options. all wake up the mcu on a high to low transition. this means if the pin is low, the i/o cannot wake-up the mcu. i/o port control registers each i/o port has its own control register pac, pbc, pcc and pdc, to control the input/output configuration. with this control register, each cmos output or input with or without pull-high resistor structures can be reconfig - ured dynamically under software control. each of the i/o ports is directly mapped to a bit in its associated port con - trol register. note that pa pins can be setup to have nmos outputs using configuration options. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 212 . this v d d m u x m u x e n ( p w m 0 , p w m 1 ) c o n t r o l b i t d a t a b u s w r i t e c o n t r o l r e g i s t e r c h i p r e s e t r e a d c o n t r o l r e g i s t e r w r i t e d a t a r e g i s t e r d a t a b i t d q c k s q d q c k s q t m r 0 o r t m r 1 f o r p a 7 o r p d 0 o n l y i n t f o r p a 6 o n l y s y s t e m w a k e - u p r e a d d a t a r e g i s t e r w a k e - u p o p t i o n p u l l - h i g h p a 4 , p a 5 p w m 0 , p w m 1 p a 0 / s c s a p a 1 / s c l k a p a 2 / s d i a p a 3 / s d o a p a 4 / p w m 0 p a 5 / p w m 1 p a 6 / i n t p a 7 / t m r 0 p b 0 / a n 0 ~ p b 7 / a n 7 p c 0 / a n 8 ~ p c 7 / a n 1 5 p d 0 / t m r 1 p d 1 ~ p d 7 input/output ports
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 41 january 14, 2011 will then allow the logic state of the input pin to be di - rectly read by instructions. when the corresponding bit of the control register is written as a 202 , the i/o pin will be setup as an output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. port b vddio function the output drivers of most i/o pins use the vdd power supply line as their high voltage level. in this device pins pb0~pb6 can use a different voltage, other than vdd as their high level. this is supplied externally on pin pb7. this function is selected using configuration op - tions. pin-shared functions the flexibility of the microcontroller range is greatly en - hanced by the use of pins that have more than one func - tion. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be over - come. for some pins, the chosen function of the multi-function i/o pins is set by configuration options while for others the function is set by application pro - gram control. external interrupt input the external interrupt pin int is pin-shared with the i/o pin pa6. for applications not requiring an external interrupt input, the pin-shared external interrupt pin can be used as a normal i/o pin, however to do this, the external interrupt enable bits in the intc0 register must be disabled. external timer clock inputs the external timer pins tmr0 and tmr1 are pin-shared with i/o pins. to configure these pins to operate as timer inputs, the corresponding control bits in the timer control register must be correctly set. for applications that do not require external timer inputs, these pins can be used as normal i/o pins. note that if used as normal i/o pins the timer mode control bits in the timer control register must select the timer mode, which has an internal clock source, to prevent the in - put pin from interfering with the timer operation. pwm outputs the device contains two pwm outputs which are pin-shared with i/o pins. the pwm output functions are chosen via configuration options and remain fixed after the device is programmed. note that the corre - sponding bit of the port control register, pac, must setup the pin as an output to enable the pwm output. if the pac port control register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high option, even if the pwm con - figuration option has been selected. a/d inputs these devices can have up to 16 a/d converter inputs depending upon which package type is chosen. all of these analog inputs are pin-shared with i/o pins on port b and port c. if these pins are to be used as a/d inputs and not as normal i/o pins then the corre - sponding bits in the a/d converter control register, adcr, must be properly set. there are no configura - tion options associated with the a/d function. if used as i/o pins, then full pull-high resistor configuration options remain, however if used as a/d inputs then any pull-high resistor options associated with these pins will be automatically disconnected. i/o pin structures the vast range of i/o functions and pin-shared options results in a huge variety of i/o pin structure types. for this reason the generic input/output port diagram pro - vided here is for general reference only. as the exact logical construction of the i/o pin will differ from the drawing, they are supplied as a guide only to assist with the functional understanding of the basic i/o pins. programming considerations within the user program, one of the first things to con - sider is port initialisation. after a reset, all of the data and port control register will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. if the pac, pbc, pcc and pdc port control register, are then pro- grammed to setup some pins as outputs, these output pins will have an initial high output value unless the as- sociated pa, pb, pc and pd port data registers are first programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct value into the port control register or by program - ming individual bits in the port control register using the 2 set [m].i2 and 2 clr [m].i2 instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must first read in the data on the entire port, modify it to the re - quired new bit values and then rewrite this data back to the output ports. the ports have the additional capability of providing wake-up functions. when the device is in the power down mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port pins. single or multiple pins on the ports can be setup to have this function. t 1 t 2 t 3 t 4 t 1 t 2 t 3 t 4 w r i t e t o p o r t r e a d f r o m p o r t s y s t e m c l o c k p o r t d a t a read/write timing
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 42 january 14, 2011 timer/event counters the provision of timers form an important part of any microcontroller giving the designer a means of carrying out time related functions. the device contains two in - ternal 16-bit count-up timer which has three operating modes. the timer can be configured to operate as a general timer, external event counter or as a pulse width measurement device. the provision of an internal 16-stage prescaler on one of the timers clock circuitry gives added range to the timer. there are two types of registers related to the timer/event counters. the first is the register that con - tain the actual value of the timer/event counter and into which an initial value can be preloaded, and is known as tmr0h, tmr0l, tmr1h or tmr1l. reading from this register retrieves the contents of the timer/event coun - ter. the second type of associated register is the timer control register, which defines the timer options and determines how the timer/event counter is to be used, and has the name tmr0c or tmr1c. this device can have the timer clocks configured to come from the inter - nal clock sources. in addition, the timer clock sources can also be configured to come from the external timer pins. configuring the timer/event counter input clock source the internal timers clock source can originate from a choice of internal system clocks or from an external clock source. the system clock input timer source is used when the timer is in the timer mode or in the pulse width measurement mode. the internal clock source of timer1 passes trough a prescaler or can directly come from fsys/4 using bits t1s and t1pss0/t1pss1 in the mode register. the prescaler clock source can come from either wdt osc, rtc oscillator or f sys /4. the prescaler value is condi - tioned by the bits ps1c0, ps1c1 and ps1c2 in the tmr1c register. an external clock source is used when the timer is in the event counting mode, the clock source being provided on the shared tmr0 or tmr1 pin. depending upon the condition of the t0e or t1e bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. timer register - tmr0h/tmr1h, tmr0l/tmr1l the timer registers are special function registers located in the special purpose data memory and are the places where the actual timer values are stored. the timer reg - isters are known as tmr0l, tmr0h, tmr1l and tmr1h. the value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the external timer pin. the timer will count from the initial value loaded by the preload register to the full count of ffffh for the 16-bit timer at which point the timer overflows and an internal interrupt signal is generated. the timer value will then be reset with the initial preload register value and con- tinue counting. t i m e r / e v e n t c o u n t e r m o d e c o n t r o l 1 6 - b i t p r e l o a d r e g i s t e r d a t a b u s r e l o a d o v e r f l o w t o i n t e r r u p t l o w b y t e b u f f e r t 1 m 1 t 1 m 0 t 1 o n h i g h b y t e l o w b y t e 1 6 - b i t t i m e r / e v e n t c o u n t e r t m r 1 t 1 e f s y s / 4 r t c o s c i l l a t o r 8 - s t a g e p r e s c a l e r p s c i c 2 ~ p s c i c 0 w d t o s c m u x t 1 s t 1 p s s 0 m u x t 1 p s s 1 f s y s / 4 16-bit timer/event counter 1 structure t m r 0 t 0 e t i m e r / e v e n t c o u n t e r m o d e c o n t r o l 1 6 - b i t p r e l o a d r e g i s t e r d a t a b u s r e l o a d o v e r f l o w t o i n t e r r u p t l o w b y t e b u f f e r t 0 m 1 t 0 m 0 t 0 o n h i g h b y t e l o w b y t e 1 6 - b i t t i m e r / e v e n t c o u n t e r f s y s / 4 16-bit timer/event counter 0 structure
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 43 january 14, 2011 to achieve a maximum full range count of ffffh, the preload registers must first be cleared to all zeros. it should be noted that after power-on, the preload register will be in an unknown condition. note that if the timer/event counter is switched off and data is written to its preload registers, this data will be immediately writ - ten into the actual timer registers. however, if the timer/event counter is enabled and counting, any new data written into the preload data registers during this period will remain in the preload registers and will only be written into the timer registers the next time an over - flow occurs. for 16-bit timer/event counters which have both low byte and high byte timer registers, accessing these reg - isters is carried out in a specific way. it must be note when using instructions to preload data into the low byte timer register, namely tmr1l, the data will only be placed in a low byte buffer and not directly into the low byte timer register. the actual transfer of the data into the low byte timer register is only carried out when a write to its associated high byte timer register, namely tmr1h, is executed. on the other hand, using instruc - tions to preload data into the high byte timer register will result in the data being directly written to the high byte timer register. at the same time the data in the low byte buffer will be transferred into its associated low byte timer register. for this reason, the low byte timer register should be written first when preloading data into the 16-bit timer registers. it must also be noted that to read the contents of the low byte timer register, a read to the high byte timer register must be executed first to latch the contents of the low byte timer register into its associ- ated low byte buffer. after this has been done, the low byte timer register can be read in the normal way. note that reading the low byte timer register will result in read - ing the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. timer control register - tmr0c/tmr1c the flexible features of the holtek microcontroller timer/event counters enable them to operate in three different modes, the options of which are determined by the contents of the timer control register tmr0c/ tmr1c. together with the tmr0l/tmr1l and tmr0h/ tmr1h registers, these three registers control the full operation of the timer/event counter. before the timer can be used, it is essential that the tmr0c/tmr1c reg - ister is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. to choose which of the three modes the timer is to oper - ate in, the timer mode, the event counting mode or the pulse width measurement mode, bits t0m0/t1m0 and t0m1/t1m1 must be set to the required logic levels. the timer-on bit t0on/t1on or bit 4 of the tmr0c/tmr1c register provides the basic on/off control of the timer, setting the bit high allows the counter to run, clearing the bit stops the counter. if the timer is in the event count or pulse width measurement mode the active transition edge level type is selected by the logic level of the t0e/t1e or bit 3 of the tmr0c/tmr1c register. configuring the timer mode in this mode, the timer/event counter can be utilised to measure fixed time intervals, providing an internal inter - rupt signal each time the timer/event counter over - flows. to operate in this mode, the operating mode select bit pair, t0m1/t0m0 or t1m1/t1m0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the timer mode bit7 bit6 1 0 in this mode the internal clock, f sys /4 is used as the inter- nal clock for the timer/event counter. after the other bits in the timer control register have been setup, the enable bit t0on or t1on, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. each time an internal clock cycle occurs, the timer/event counter increments by one. when it is full and overflows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and con - tinue counting. the interrupt can be disabled by ensur - ing that the timer/event counter interrupt enable bit in the interrupt control register, intc, is reset to zero. i n c r e m e n t t i m e r c o n t r o l l e r p r e s c a l e r o u t p u t t i m e r + 1 t i m e r + 2 t i m e r + n t i m e r + n + 1 timer mode timing chart
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 44 january 14, 2011 n o t i m p l e m e n t e d , r e a d a s " 0 " e v e n t c o u n t e r a c t i v e e d g e s e l e c t 1 : c o u n t o n f a l l i n g e d g e 0 : c o u n t o n r i s i n g e d g e t i m e r / e v e n t c o u n t e r c o u n t i n g e n a b l e 1 : e n a b l e 0 : d i s a b l e o p e r a t i n g m o d e s e l e c t t 0 m 1 0 0 1 1 t 0 m 0 0 1 0 1 n o m o d e a v a i l a b l e e v e n t c o u n t e r m o d e t i m e r m o d e p u l s e w i d t h m e a s u r e m e n t m o d e n o t i m p l e m e n t e d , r e a d a s " 0 " b 7 t 0 e t 0 o n t 0 m 0 t 0 m 1 b 0 t m r 0 c r e g i s t e r timer/event counter 0 control register b 7 t 1 e t 1 o n t 1 m 0 t 1 m 1 b 0 p s 1 c 2 p s 1 c 1 p s 1 c 0 e v e n t c o u n t e r a c t i v e e d g e s e l e c t 1 : c o u n t o n f a l l i n g e d g e 0 : c o u n t o n r i s i n g e d g e p u l s e w i d t h m e a s u r e m e n t a c t i v e e d g e s e l e c t 1 : s t a r t c o u n t i n g o n r i s i n g e d g e , s t o p o n f a l l i n g e d g e 0 : s t a r t c o u n t i n g o n f a l l i n g e d g e , s t o p o n r i s i n g e d g e t i m e r / e v e n t c o u n t e r c o u n t i n g e n a b l e 1 : e n a b l e 0 : d i s a b l e n o t i m p l e m e n t e d , r e a d a s " 0 " o p e r a t i n g m o d e s e l e c t t 1 m 1 t 1 m 0 0 0 n o m o d e a v a i l a b l e 0 1 e v e n t c o u n t e r m o d e 1 0 t i m e r m o d e 1 1 p u l s e w i d t h m e a s u r e m e n t m o d e t i m e r p r e s c a l e r r a t e s e l e c t p s 1 c 2 0 0 0 0 1 1 1 1 p s 1 c 1 0 0 1 1 0 0 1 1 p s 1 c 0 0 1 0 1 0 1 0 1 f s p = f s / 3 2 f s p = f s / 6 4 f s p = f s / 1 2 8 f s p = f s / 2 5 6 f s p = f s / 5 1 2 f s p = f s / 1 0 2 4 f s p = f s / 2 0 4 8 f s p = f s / 4 0 9 6 t m r 1 c r e g i s t e r timer/event counter 1 control register
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 45 january 14, 2011 configuring the event counter mode in this mode, a number of externally changing logic events, occurring on the external timer pin, can be re - corded by the timer/event counter. to operate in this mode, the operating mode select bit pair, t0m1/t0m0 or t1m1/t1m0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the event counter mode bit7 bit6 0 1 in this mode, the external timer pin, tmr0 or tmr1, is used as the timer/event counter clock source, however it is not divided by the internal prescaler. after the other bits in the timer control register have been setup, the enable bit t0on or t1on, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. if the active edge select bit t0e or t1e, which is bit 3 of the timer control register, is low, the timer/event counter will increment each time the external timer pin receives a low to high transition. if the active edge select bit is high, the counter will incre - ment each time the external timer pin receives a high to low transition. when it is full and overflows, an interrupt signal is generated and the timer/event counter will re - load the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the interrupt control register, intc, is reset to zero. as the external timer pin is an independent pin and not shared with an i/o pin, the only thing to ensure the timer operate as an event counter is to ensure that the oper- ating mode select bits in the timer control register place the timer/event counter in the event counting mode. it should be noted that in the event counting mode, even if the microcontroller is in the power down mode, the timer/event counter will continue to record externally changing logic events on the timer input pin. as a result when the timer overflows it will generate a timer interrupt and corresponding wake-up source. configuring the pulse width measurement mode in this mode, the timer/event counter can be utilised to measure the width of external pulses applied to the ex - ternal timer pin. to operate in this mode, the operating mode select bit pair, t0m1/t0m0 or t1m1/t1m0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the pulse width measurement mode bit7 bit6 1 1 in this mode the internal clock, f sys /4 is used as the inter - nal clock for the 16-bit timer/event counter 0. the t1s and t1pss0/t1pss1 bits select the internal clock for the 16-bit timer/event counter 1. after the other bits in the timer control register have been setup, the enable bit t0on or t1on, which is bit 4 of the timer control register, can be set high to enable the timer/event counter, however it will not actually start counting until an active edge is received on the external timer pin. if the active edge select bit t0e or t1e, which is bit 3 of the timer control register, is low, once a high to low transition has been received on the external timer pin, tmr0 or tmr1, the timer/event counter will start counting until the external timer pin returns to its original high level. at this point the enable bit will be automati- cally reset to zero and the timer/event counter will stop counting. if the active edge select bit is high, the timer/event counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin re- turns to its original low level. as before, the enable bit will be automatically reset to zero and the timer/event counter will stop counting. it is important to note that in the pulse width measurement mode, the enable bit is + 1 + 2 + 3 + 4 t i m e r e x t e r n a l t i m e r p i n i n p u t t 0 o n o r t 1 o n ( w i t h t 0 e o r t 1 e = 0 ) p r e s c a l e r o u t p u t i n c r e m e n t t i m e r c o u n t e r p r e s c a l e r o u t p u t i s s a m p l e d a t e v e r y f a l l i n g e d g e o f t 1 . pulse width measure mode timing chart t i m e r + 2 e x t e r n a l e v e n t i n c r e m e n t t i m e r c o u n t e r t i m e r + 3 t i m e r + 1 event counter mode timing chart
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 46 january 14, 2011 automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. the residual value in the timer/event counter, which can now be read by the program, therefore represents the length of the pulse received on the external timer pin. as the enable bit has now been reset, any further transitions on the external timer pin will be ignored. not until the enable bit is again set high by the program can the timer begin further pulse width measurements. in this way, single shot pulse measurements can be easily made. it should be noted that in this mode the timer/event counter is controlled by logical transitions on the exter - nal timer pin and not by the logic level. when the timer/event counter is full and overflows, an interrupt signal is generated and the timer/event counter will re - load the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the interrupt control register, intc, is reset to zero. as the external timer pin is an independent pin and not shared with an i/o pin, the only thing to ensure the timer operate in pulse width measurement mode is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the pulse width measurement mode. prescaler bits ps1c0~ps1c2 of the tmr1c register are used to define the pre-scaling stages of the internal clock source of the timer/event counter 1. i/o interfacing the timer/event counter, when configured to run in the event counter or pulse width measurement mode, re - quire the use of external pins for correct operation. as these pins are shared pins they must be configured cor - rectly to ensure they are setup for use as timer/event counter inputs and not as a normal i/o pins. this is im - plemented by ensuring that the mode select bits in the timer/event counter control register, select either the event counter or pulse width measurement mode. addi - tionally the relevant port control register for this pin must be set high to ensure that the pin is setup as an in - put. any pull-high resistor configuration option on this pin will remain valid even if the pin is used as a timer/event counter input. programming considerations when configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. in this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respec - tive internal interrupt vector. for the pulse width mea - surement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not synchronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a result, there may be small differences in measured values requiring programmers to take this into account during programming. the same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. when the timer/event counter is read, or if data is writ - ten to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. care must be taken to ensure that the timers are prop - erly initialised before using them for the first time. the associated timer enable bits in the interrupt control reg - ister must be properly set otherwise the internal interrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. it is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. after the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control regis - ter. note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction.
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 47 january 14, 2011 when the timer/event counter overflows, its corre - sponding interrupt request flag in the interrupt control register will be set. if the timer interrupt is enabled this will in turn generate an interrupt signal. however irre - spective of whether the interrupts are enabled or not, a timer/event counter overflow will also generate a wake-up signal if the device is in a power-down condi - tion. this situation may occur if the timer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the timer/event counter will continue to count these exter - nal events and if an overflow occurs the device will be woken up from its power-down condition. to prevent such a wake-up from occurring, the timer interrupt re - quest flag should first be set high before issuing the 2 halt2 instruction to enter the power down mode. timer program example this program example shows how the timer/event counter registers are setup, along with how the inter - rupts are enabled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counter to be in the timer mode, which uses the internal system clock as the clock source. org 04h ; usb interrupt vector reti org 0ch ; timer/event counter 0 interrupt vector jmp tmrint ; jump here when timer overflows : org 20h ; main program ;internal timer/event counter 0 interrupt routine tmrint: : ; timer/event counter main program placed here : reti : : begin: ;setup timer registers mov a,09bh ; setup timer preload value mov tmr0l,a; mov a,0ffh ; setup timer preload value mov trm0h,a mov a,080h ; setup timer control register mov tmr0c,a ; timer mode ; setup interrupt register mov a,009h ; enable master interrupt and timer interrupt mov intc0,a set tmr0c.4 ; start timer/event counter - note mode bits must be previously setup
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 48 january 14, 2011 a u t o m a t i c a l l y c l e a r e d b y i s r m a n u a l l y s e t o r c l e a r e d b y s o f t w a r e u s b i n t e r r u p t r e q u e s t f l a g u s b f _ a e u i e m i p r i o r i t y i n t e r r u p t p o l l i n g h i g h a u t o m a t i c a l l y d i s a b l e d b y i s r c a n b e e n a b l e d m a n u a l l y t i m e r / e v e n t c o u n t e r 0 o v e r f l o w i n t e r r u p t r e q u e s t f l a g t f 0 e e i l o w e s i i _ b s p i _ b i n t e r r u p t r e q u e s t f l a g s i f _ b s p i _ a i n t e r r u p t r e q u e s t f l a g s i f _ a e s i i _ a t i m e r / e v e n t c o u n t e r 1 o v e r f l o w i n t e r r u p t r e q u e s t f l a g t f 1 e x t e r n a l i n t e r r u p t r e q u e s t f l a g e i f e t i 0 e t i 1 interrupt structure interrupts interrupts are an important part of any microcontroller system. when an external interrupt pin transition or an internal function such as a timer/event counter over - flow, an usb interrupt, or transmission or reception of spi data occurs, their corresponding interrupt will en - force a temporary suspension of the main program al - lowing the microcontroller to direct attention to their respective needs. each device contains two external in - terrupts and several internal interrupts functions. the external interrupt is controlled by the action of the exter - nal interrupt pins, while the internal interrupts are con - trolled by the timer/event counter overflow, a usb interrupt and spi data transmission or reception. interrupt registers overall interrupt control, which means interrupt enabling and request flag setting, is controlled by the two inter - rupt control registers, which are located in the data memory. by controlling the appropriate enable bits in these registers each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corre - sponding request flag will be set by the microcontroller. the global enable flag if cleared to zero will disable all interrupts. interrupt operation a usb interrupt , a timer/event counter overflow, 8-bits of data transmission or reception on either of the spi in - terfaces or an active edge on external interrupt pin will all generate an interrupt request by setting their corre- sponding request flag, if their appropriate interrupt en- able bit is set. when this happens, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new ad - dress which will be the value of the corresponding inter - rupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp statement which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti statement, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their as - sociated request flags, are shown in the accompanying diagram with their order of priority. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked, as the emi bit will be cleared au - tomatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests oc - cur during this interval, although the interrupt will not be immediately serviced, the request flag will still be re - corded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the rou - tine, to allow interrupt nesting. if the stack is full, the in - terrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full.
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 49 january 14, 2011 i n t c 1 r e g i s t e r s p i s e r i a l i n t e r f a c e a i n t e r r u p t e n a b l e 1 : e n a b l e 0 : d i s a b l e s p i s e r i a l i n t e r f a c e b i n t e r r u p t e n a b l e 1 : e n a b l e 0 : d i s a b l e t i m e r / e v e n t c o u n t e r 1 i n t e r r u p t e n a b l e 1 : e n a b l e 0 : d i s a b l e n o t i m p l e m e n t e d , r e a d a s " 0 " s p i s e r i a l i n t e r f a c e a d a t a t r a n s f e r r e d o r d a t a r e c e i v e d i n t e r r u p t r e q u e s t f l a g 1 : a c t i v e 0 : i n a c t i v e s p i s e r i a l i n t e r f a c e b d a t a t r a n s f e r r e d o r d a t a r e c e i v e d i n t e r r u p t r e q u e s t f l a g 1 : a c t i v e 0 : i n a c t i v e t i m e r / e v e n t c o u n t e r 1 i n t e r r u p t r e q u e s t f l a g 1 : a c t i v e 0 : i n a c t i v e n o t i m p l e m e n t e d , r e a d a s " 0 " b 7 b 0 e t i 1 e s i i _ b e s i i _ a s i f _ a s i f _ b t f 1 intc1 register i n t c 0 r e g i s t e r m a s t e r i n t e r r u p t g l o b a l e n a b l e 1 : g l o b a l e n a b l e 0 : g l o b a l d i s a b l e u s b i n t e r r u p t e n a b l e 1 : e n a b l e 0 : d i s a b l e e x t e r n a l i n t e r r u p t e n a b l e 1 : e n a b l e 0 : d i s a b l e t i m e r / e v e n t c o u n t e r 0 i n t e r r u p t e n a b l e 1 : e n a b l e 0 : d i s a b l e u s b i n t e r r u p t r e q u e s t f l a g 1 : a c t i v e 0 : i n a c t i v e e x t e r n a l i n t e r r u p t r e q u e s t f l a g 1 : a c t i v e 0 : i n a c t i v e t i m e r / e v e n t c o u n t e r 0 i n t e r r u p t r e q u e s t f l a g 1 : a c t i v e 0 : i n a c t i v e f o r t e s t m o d e u s e d o n l y m u s t b e w r i t t e n a s " 0 " ; o t h e r w i s e m a y r e s u l t i n u n p r e d i c t a b l e o p e r a t i o n b 7 b 0 e e i e u i e m i e i ft f 0 e t i 0 u s b f intc0 register
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 50 january 14, 2011 interrupt priority interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector usb interrupt 1 0004h external interrupt 2 0008h timer/event counter 0 overflow interrupt 3 000ch spi_a interrupt 4 0010h spi_b interrupt 5 0014h timer/event counter 1 overflow interrupt 6 0018h suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occur - rences. external interrupt for an external interrupt to occur, the global interrupt en - able bit, emi, and external interrupt enable bit, eei, must first be set. an actual external interrupt will take place when the external interrupt request flag, eif is set, a situation that will occur when a high to low transition appears on the interrupt pins. the external interrupt pin is pin-shared with the i/o pins pa6 can only be config- ured as an external interrupt pin if the corresponding ex- ternal interrupt enable bits in the interrupt control register intc0 have been set. the pins must also be setup as inputs by setting the corresponding pac.6 bits in the port control register. when the interrupt is en - abled, the stack is not full and a high to low transition ap - pears on the external interrupt pin, a subroutine call to the external interrupt vector at location 08h will take place. when the interrupt is serviced, the external inter - rupt request flag, eif will be automatically reset and the emi bit will be automatically cleared to disable other in - terrupts. note that any pull-high resistor configuration options on these pins will remain valid even if the pins are used as external interrupt inputs. timer/event counter interrupt for a timer/event counter interrupt to occur, the global interrupt enable bit, emi, and the corresponding timer interrupt enable bit, eti0 or eti1, must first be set. an actual timer/event counter interrupt will take place when the timer/event counter interrupt request flag, tf0 or tf1, is set, a situation that will occur when the timer/event counter overflows. when the interrupt is enabled, the stack is not full and a timer/event counter overflow occurs, a subroutine call to the timer interrupt vector at location 0ch or 018h, will take place. when the interrupt is serviced, the timer interrupt request flag, tf0 or tf1, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. spi interrupt for an spi interrupt to occur, the global interrupt enable bit, emi, and the corresponding spi interrupt enable bit, esii_a or esii_b, must be first set. an actual spi inter - rupt will take place when one of the two spi interrupt re - quest flags, sif_a or sif_b, are set, a situation that will occur when 8-bits of data are transferred or received from either of the spi interfaces. when the interrupt is enabled, the stack is not full and an spi_a interrupt oc - curs, a subroutine call to the spi_a interrupt vector at lo - cation 10h, will take place. for an spi_b interrupt, a subroutine call to the spi_b interrupt vector at location 14h, will take place. when the interrupt is serviced, the spi interrupt request flag, sif_a or sif_b, will be auto - matically reset and the emi bit will be automatically cleared to disable other interrupts. usb interrupt a usb interrupts will be triggered by the following usb events, at which point the the related interrupt request flag, usbf in the intc0 register, will be set. accessing the corresponding usb fifo from the pc a usb suspend signal from the pc a usb resume signal from the pc a usb reset signal when the interrupt is enabled, the stack is not full and the usb interrupt is active, a subroutine call to location 04h will occur. the interrupt request flag, usbf, and the emi bit will be cleared to disable other interrupts. when pc host accesses the fifo of the device, the corresponding request usr bit is set, and a usb inter - rupt is triggered. therefore it can be determined which fifo has been accessed. when the interrupt has been served, the corresponding bit should be cleared by the program. when the device receive a usb suspend sig - nal from the host pc, the suspend line, bit0 of usc, is set and a usb interrupt is also triggered. also when de - vice receive a resume signal from the host pc, the re - sume line, bit3 of usc, is set and a usb interrupt is triggered. programming considerations by disabling the interrupt enable bits, a requested inter - rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt control register until the corre - sponding interrupt is serviced or until the request flag is cleared by a software instruction.
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 51 january 14, 2011 it is recommended that programs do not use the 2call subroutine2 instruction within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt is not well con - trolled, the original control sequence will be damaged once a 2 call subroutine2 is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the power down mode. only the program counter is pushed onto the stack. if the contents of the accumulator or status register are al - tered by the interrupt service program, which may cor - rupt the desired control sequence, then the contents should be saved in advance. reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, af - ter a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program com - mences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is force - fully pulled low. in such a case, known as a normal oper - ation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of re - set operations result in different register conditions be - ing setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is imple - mented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and ex - ternally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. as well as ensuring that the program memory begins execution from the first memory ad - dress, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing a proper reset operation. in such cases it is recom - mended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected be- tween vss and the res pin will provide a suitable ex- ternal reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset cir - cuit shown is recommended. more information regarding external reset circuits is located in application note ha0075e on the holtek website. r e s v d d s s t t i m e - o u t i n t e r n a l r e s e t 0 . 9 v d d t r s t d power-on reset timing chart r e s v d d v s s 0 . 1 m f 1 0 0 k w basic reset circuit r e s 0 . 1 m f 1 0 0 k w v d d v s s 0 . 0 1 m f 1 0 k w enhanced reset circuit
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 52 january 14, 2011 res pin reset this type of reset occurs when the microcontroller is already running and the res pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initi - ated from this point. note that as the external reset pin is also pin-shared with pa7, if it is to be used as a reset pin, the correct reset configuration option must be se - lected. low voltage reset - lvr the microcontroller contains a low voltage reset cir - cuit in order to monitor the supply voltage of the de - vice. the lvr function is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally. for a valid lvr signal, a low sup - ply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that spec - ified by t lvr in the a.c. characteristics. if the low sup - ply voltage state does not exceed this value, the lvr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be se- lected via configuration options. watchdog time-out reset during normal operation the watchdog time-out reset during normal opera - tion is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to 212. watchdog time-out reset during power down the watchdog time-out reset during power down is a little different from other kinds of reset. most of the conditions remain unchanged except that the pro - gram counter and the stack pointer will be cleared to 202 and the to flag will be set to 212 . refer to the a.c. characteristics for t sst details. reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the power down function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 res reset during power-on 0 0 res wake-up during power down 0 0 res or lvr reset during normal operation 1 u wdt time-out reset during normal operation 1 1 wdt time-out reset during power down note: 2u2 stands for unchanged the following table indicates the way in which the vari- ous components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer/event counter timer counter will be turned off prescaler the timer counter prescaler will be cleared input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack w d t t i m e - o u t s s t t i m e - o u t i n t e r n a l r e s e t t r s t d wdt time-out reset during normal operation timing chart w d t t i m e - o u t s s t t i m e - o u t t s s t wdt time-out reset during power down timing chart r e s s s t t i m e - o u t i n t e r n a l r e s e t 0 . 9 v d d 0 . 4 v d d t r s t d res reset timing chart l v r s s t t i m e - o u t i n t e r n a l r e s e t t r s t d low voltage reset timing chart
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 53 january 14, 2011 the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects the microcontroller in - ternal registers. register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb reset (normal) usb reset (halt) mp0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx mp1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu wdts ---- -111 ---- -111 ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu status --00 xxxx --1u uuuu --00 uuuu --00 uuuu --11 uuuu --uu uuuu --01 uuuu intc0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 tmr1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tmr1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tmr1c 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- uu-u u--- uu-u u--- tmr0h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx tmr0l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx tmr0c 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- uu-u u--- uu-u u--- pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 usb_stat --xx 0000 --xx 0000 --xx 0000 --xx 0000 --xx 0000 --xx 0000 --xx 0000 uint 0000 1111 0000 uuuu 0000 1111 0000 1111 0000 uuuu 0000 1111 0000 1111 intc1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu -000 -000 -000 -000 tbhp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu usc 1000 0000 uuuu xuux 1000 0000 1000 0000 uuuu xuux 1uuu 0100 1uuu 0100 usr ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 ucc 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0uu0 u000 0uu0 u000 awr 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 stall ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 sies 00-0 0000 uu-x xuuu 00-0 0000 00-0 0000 uu-x uuuu 00-0 0000 00-0 0000 misc 0000 0000 xxuu uuuu 0000 0000 0000 0000 xxuu uuuu 0000 0000 0000 0000 ufien ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 fifo0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 54 january 14, 2011 register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb reset (normal) usb reset (halt) fifo1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo3 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ufoen ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 ufc0 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 sbcra 0110 0000 0110 0000 0110 0000 0110 0000 uuuu uuuu uuuu uuuu uuuu uuuu sbdra uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu adrl xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu ---- xxxx ---- xxxx ---- adrh xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx xxxx xxxx adcr 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu 0100 0000 0100 0000 acsr 0--- --00 0--- --00 0--- --00 ---- --00 u--- --uu 1--- --00 ---- --00 sbcrb 0110 0000 0110 0000 0110 0000 0110 0000 uuuu uuuu uuuu uuuu uuuu uuuu sbdrb uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mode xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx spi_reg 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pwmbr0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pwm0dr 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pwmbr1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pwm1dr 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pwmctl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 note: 2*2 means 2warm reset2, 2-2 not implemented 2u2 means 2unchanged2, 2x2 means 2unknown2
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 55 january 14, 2011 oscillator these devices provide two types of system oscillator cir - cuits, an 6mhz or 12mhz crystal oscillator and a 32768hz crystal oscillator, the choice of which is deter - mined by software. to use the 6mhz or 12mhz oscillator, a suitable crystal is connected between osc1 and osc2. it is a default option at ic power-on. the other oscillator circuit is de - signed for the real time clock. for this device, only a 32768hz crystal oscillator can be used. the crystal should be connected between osc3 and osc4. this oscillator is designed for system clocks. the power-down mode stops the system oscillator to con - serve power. a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator. no other external components are required. in stead of a crystal, a resonator can also be connected between osc1 and osc2 to get a frequency reference, but two external capacitors in osc1 and osc2 may be re - quired. the devices can operate only with 6mhz or 12mhz sys- tem clocks. in order to ensure that the usb sie func- tions properly, users should correctly configure the sclksel bit of the scc register. the default system clock is 12mhz. rtc oscillator when the device enter a power-down condition, the in - ternal clocks are normally switched off to stop microcontroller activity and to conserve power. how - ever, in many microcontroller applications it may be nec - essary to keep some internal functions operational, such as timers, even when the microcontroller is in the power-down mode. to provide this feature, this device incorporates an rtc oscillator, which will remain active at all times, even when the microcontroller is in the power down condition. this clock source has a fixed fre - quency of 32768hz and requires a 32768hz crystal to be connected between pins osc3 and osc4. the rtc oscillator circuit enable/disable is controlled by the f32k_dis bit in the mode register. an additional bit f32k_ctrl enables the rtc oscillator to be powered up quickly. watchdog timer oscillator the wdt oscillator is a fully self-contained free running on-chip rc oscillator with a typical period of 65 m s at 5v requiring no external components. when the device en - ters the power down mode, the system clock will stop running but the wdt oscillator continues to free-run and to keep the watchdog active. however, to preserve power in certain applications the wdt oscillator can be disabled via a configuration option. operation mode the device supports two system clocks: a high fre - quency system clock (6mhz, 12mhz) or a low system clock, 32768hz. there is a single register that deter - mines how to define which system mode is in operation. the system clock is changed as shown in the following procedure. from high frequency to low frequency: set mods to 212 wait a delay time - 400ms if the 32k oscillator is off, no delay if the if the 32k oscillator is on the mcu will switch to the low frequency 32768hz oscillator and turn-off the high frequency system clock from low frequency to high frequency: set hfreq_en to 212 to turn-on the high frequency os - cillator wait a delay time to make sure that the high frequency oscillator is stable - 5ms set mods to 202 the mcu will switch to the high frequency oscillator but the 32768hz oscillator will continue to oscillate. o s c 2 o s c 1 crystal oscillator o s c 4 o s c 3 crystal/ceramic oscillator l o w s p e e d o p e r a t i o n m o d e = 1 h f r e q = 0 h i g h s p e e d o p e r a t i o n m o d e = 0 h f r e q = 1 s e t h f r e q t o " 1 " d e l a y f o r c l o c k t o s t a b i l i s e c l e a r m o d s t o " 0 " s e t m o d s t o " 1 " d e l a y i s 3 2 k o s c i l l a t o r o f f h f r e q a u t o c l e a r e d t o " 0 " mode switching
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 56 january 14, 2011 bit no. label function 0 mods high/low frequency system clock select bit 0: high frequency system clock - 6mhz or 12mhz select - default 1: 32768hz system clock select 1 hfreq_en 1: enable high frequency system clock, hardware will automatically clear this bit when mods switches from low to high 2 f32k_dis 1: disable 32768hz oscillator - default enable 0: enable 32768hz oscillator 3 2.2lvd 1: v dd < 2.2v 0: v dd > 2.2v 4 5 t1pss0 t1pss1 timer/event counter 1 clock source select 00: rtc (default) 01: f sys /4 10: wdt osc 11: no source 6 t1s timer/event counter 1 clock source select 0: f sys /4 (default) 1: timer1 prescaler output 7 f32k_ctrl rtc oscillator quick start function 1: quick start enabled 0: quick start disabled - lower operating current this bit will set by the hardware during power on, once the 32k oscillator is stable the bit can be cleared by the application program to reduce power consumption. mode (40h) register power down mode and wake-up power down mode all of the holtek microcontrollers have the ability to enter a power down mode. when the device enters this mode, the normal operating current, will be reduced to an ex- tremely low standby current level. this occurs because when the device enters the power down mode, the sys - tem oscillator is stopped which reduces the power con - sumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. this feature is extremely important in applica - tion areas where the microcontroller must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. entering the power down mode there is only one way for the device to enter the power down mode and that is to execute the 2 halt2 instruc - tion in the application program. when this instruction is executed, the following will occur: the system oscillator will stop running and the appli - cation program will stop at the 2halt2 instruction. if the rtc oscillator configuration option is enabled then the rtc clock will keep running. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the wdt or rtc oscillator. the wdt will stop if its clock source originates from the system clock. the i/o ports will maintain their present condition. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the power down mode is to keep the current consumption of the microcontroller to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit de - signer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be con - nected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or con - nected only to external circuits that do not draw current, such as other cmos inputs.
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 57 january 14, 2011 if the configuration options have enabled the watchdog timer internal oscillator then this will continue to run when in the power down mode and will thus consume some power. for power sensitive applications it may be therefore preferable to use the system clock source for the watchdog timer. if any i/o pins are configured as a/d analog inputs using the channel configuration bits in the adcr register, then the a/d converter will be turned on and a certain amount of power will be consumed. it may be therefore desirable before entering te power down mode to ensure that the a/d converter is powered down by ensuring that any a/d input pins are setup as normal logic inputs with pull-high resistors. wake-up after the system enters the power down mode, it can be woken up from one of various sources listed as follows: an external reset an external falling edge on any of the i/o pins a system interrupt a wdt overflow if the system is woken up by an external reset, the de - vice will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the ac - tual source of the wake-up can be determined by exam - ining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the 2 halt2 instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status. each pins on port a or any nibble on the other ports can be setup via an individual configuration option to permit a negative transition on the pin to wake-up the system. when a port pins wake-up occurs, the program will re - sume execution at the instruction following the 2 halt2 instruction. if the system is woken up by an interrupt, then two possi - ble situations may occur. the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume exe - cution at the instruction following the 2 halt2 instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be ser - viced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set to 212 be - fore entering the power down mode, the wake-up func - tion of the related interrupt will be disabled. no matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal sys - tem operation resumes. however, if the wake-up has originated due to an interrupt, the actual interrupt sub - routine execution will be delayed by an additional one or more cycles. if the wake-up results in the execution of the next instruction following the 2 halt2 instruction, this will be executed immediately after the 1024 system clock period delay has ended. low voltage detector - lvd this low voltage detect internal function provides a means for the user to monitor when the power supply voltage falls below a certain fixed level as specified in the dc characteristics. the lvd is enabled using a con - figuration option. bit 3 of the mode register is used to monitor the overall function of the lvd. under normal operation, and when the power supply voltage is above the specified vlvd value in the dc characteristic sec - tion, the 2.2lvd bit will remain at a zero value. if the power supply voltage should fall below this vlvd value then the 2.2lvd bit will change to a high value indicating a low voltage condition. note that the lvdo bit is a read-only bit. by polling the 2.2lvd bit in the mode reg - ister, the application program can therefore determine the presence of a low voltage condition. it is important not to confuse the lvd with the lvr func - tion. in the lvr function an automatic reset will be gen- erated by the microcontroller, whereas in the lvd function only the 2.2lvd bit will be affected with no influ- ence on other microcontroller functions. watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown lo - cations, due to certain uncontrollable external events such as electrical noise. it operates by providing a de - vice reset when the wdt counter overflows. the wdt clock is supplied by one of two sources selected by con - figuration option: its own self-contained dedicated inter - nal wdt oscillator, or the instruction clock which is the system clock divided by 4. note that if the wdt configu - ration option has been disabled, then any instruction re - lating to its operation will result in no operation. the internal wdt oscillator has an approximate period of 32 m s at a supply voltage of 5v. if selected, it is first di - vided by 256 via an 8-stage counter to give a nominal period of 8ms. note that this period can vary with vdd, temperature and process variations. for longer wdt time-out periods the wdt prescaler can be utilized. by writing the required value to bits 0, 1 and 2 of the wdts register, known as ws0, ws1 and ws2, longer time-out periods can be achieved. with ws0, ws1 and ws2 all
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 58 january 14, 2011 equal to 212 , the division ratio is 1:128 which gives a maximum time-out period of about 1.0s. a configuration option can select the instruction clock, which is the system clock divided by 4, as the wdt clock source instead of the internal wdt oscillator. if the in - struction clock is used as the clock source, it must be noted that when the system enters the power down mode, as the system clock is stopped, then the wdt clock source will also be stopped. therefore the wdt will lose its protecting purposes. in such cases the sys - tem cannot be restarted by the wdt and can only be re - started using external signals. for systems that operate in noisy environments, using the internal wdt oscillator is therefore the recommended choice. under normal program operation, a wdt time-out will initialise a device reset and set the status bit to. how - ever, if the system is in the power down mode, when a wdt time-out occurs, only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the wdt and the wdt prescaler. the first is an external hardware reset, which means a low level on the res pin, the second is using the watchdog software instructions and the third is via a 2 halt2 instruction. there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by configuration option. the first option is to use the sin - gle 2 clr wdt2 instruction while the second is to use the two commands 2 clr wdt12 and 2 clr wdt22 . for the first option, a simple execution of 2 clr wdt2 will clear the wdt while for the second option, both 2clr wdt12 and 2 clr wdt22 must both be executed to successfully clear the wdt. note that for this second option, if 2 clr wdt12 is used to clear the wdt, suc - cessive executions of this instruction will have no effect, only the execution of a 2 clr wdt22 instruction will clear the wdt. similarly, after the 2 clr wdt22 instruc- tion has been executed, only a successive 2 clr wdt12 instruction can clear the watchdog timer. pulse width modulator the device is provided with two pulse width modulator, pwm, outputs. the internal pwm function within the de - vice is useful for applications which require functions such as motor control, heating control, illumination con - trol etc. by providing a signal of fixed frequency but of varying duty cycle on the pwm output pins, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled the choice of generated waveform is extremely flexible. pwm registers there are a total of five registers to control the pwm function. each pwm output has a pair of registers, one to control the waveform period, and another to control the duty cycle. the period control registers are known as pwmbr0 and pwmbr1 while the duty cycle regis - ters have the name pwm0dr and pwm1dr. an addi - tion register, the pwmctl register, is the control register for both outputs and contains the output en - able/disable bits and also select the pwm clock source to be either f sys or f sys /4. w s 2 w d t s r e g i s t e r b 7 b 0 w d t p r e s c a l e r r a t e s e l e c t w s 2 0 0 0 0 1 1 1 1 w s 1 0 0 1 1 0 0 1 1 w s 0 0 1 0 1 0 1 0 1 w d t r a t e 1 : 1 1 : 2 1 : 4 1 : 8 1 : 1 6 1 : 3 2 1 : 6 4 1 : 1 2 8 n o t u s e d w s 1 w s 0 watchdog timer register 8 - b i t c o u n t e r ( ? 2 5 6 ) 7 - b i t p r e s c a l e r 8 - t o - 1 m u x w d t t i m e - o u t w s 0 ~ w s 2 w d t c l o c k s o u r c e c l e a r w d t t y p e c o n f i g u r a t i o n o p t i o n c l r w d t 1 f l a g c l r w d t 2 f l a g 1 o r 2 i n s t r u c t i o n s c l r c l r f s y s / 4 w d t o s c i l l a t o r w d t c l o c k s o u r c e c o n f i g u r a t i o n o p t i o n watchdog timer
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 59 january 14, 2011 pwm operation the clock source for the pwm output is selected to be either f sys or f sys /4 using bits in the pwmctl register. the period of the pwm waveform for each pwm output is setup by programming the required value into the pwmbr0 or pwmbr1 register using the following for - mula: pwm waveform period = 256 (1/f sys )(pwmbrn+1), or 256 (4/f sys ) (pwmbrn+1) depending upon which clock source is selected. for example if the system frequency is 6mhz, if f sys /4 is selected as the pwm source clock and a decimal value of 17 is in the pwmbrn register, then the pwm wave- form will have a period of {256 (4/(610 -6 ) 18}= 3072ms which is equivalent to a frequency of 0.325khz. the duty cycle for each pwm output can be by config - ured using the pwm0dr and pwm1dr registers. the value in these registers represents the ratio of the high to low pulse in each waveform period. therefore the ra - tio of the high pulse to the low pulse, which is in fact just the duty cycle, is given by (pwmndr+1)/256. the pwm output can now be controlled using the en - able/disable bits in the ctrl register. as the pwm out - puts are pin shared with normal i/o pins they must first be setup as outputs for correct operation. when the pwm output is disabled using the enable/disable bit in the ctrl register it can still be used as a normal i/o pin. analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d con - version electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. a/d overview the device contains a multi-channel channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other con - trol signals and convert these signals directly into an 12-bit digital value. the number of available channels depends upon which package type is chosen. package channels resolution input pins 28-pin 7 12-bit pb4~pb7 pc5~pc7 32-pin 8 12-bit pb0~pb7 44-pin 16 12-bit pb0~pb7 pc0~pc7 the a/d block diagram shows the overall internal struc- ture of the a/d converter, together with its associated registers. a/d converter data registers - adrl, adrh the devices, which contain a single12-bit a/d converter, require two data registers, known as adrl and adrh . after the conversion process takes place, these regis - ters can be directly read by the microcontroller to obtain the digitised conversion value. in the following tables, d0~d7 are the a/d conversion data result bits. register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adrl d3 d2 d1 d0 ? ? ? ? adrh d11 d10 d9 d8 d7 d6 d5 d4 note: d11~d0 is the a/d conversion result data bit msb~lsb. a/d data register p w m c t l r e g i s t e r p w m 0 c l o c k s o u r c e 1 : f s y s / 4 ( d e f a u l t ) 0 : f s y s p w m 1 c l o c k s o u r c e 1 : f s y s / 4 ( d e f a u l t ) 0 : f s y s p w m e n a b l e / d i s a b l e 1 : e n a b l e 0 : d i s a b l e ( d e f a u l t ) d e s c r i b e d e l s e w h e r e 1 : u s b s i e d i s a b l e 0 : u s b s i e e n a b l e ( d e f a u l t ) n o t i m p l e m e n t e d , r e a d a s " 0 " b 7 b 0 p w m 0 _ s p w m 1 _ s p w m 0 _ e n p w m 1 _ e n u s b d i s pulse width modulator control register p w m h i g h p u l s e p w m c y c l e p e r i o d
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 60 january 14, 2011 a/d converter control register - adcr to control the function and operation of the a/d con - verter, control registers known as adcr and adsr are provided. these 8-bit registers define functions such as the selection of which analog channel is connected to the internal a/d converter, which pins are used as ana - log inputs and which are used as normal i/os as well as controlling the start function and monitoring the a/d con - verter end of conversion status. one section of this register contains the bits acs3~acs0 which define the channel number. as each of the devices contains only one actual analog to digital converter circuit, each of the individual analog inputs must be routed to the converter. it is the function of the acs3~acs0 bits in the adcr register to determine which analog channel is actually connected to the inter - nal a/d converter. the start bit in the adcr register is used to start and reset the a/d converter. when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the start bit is brought from low to high but not low again, the eocb bit in the adcr register will be set to a 212 and the analog to digital converter will be reset. it is the start bit that is used to control the overall on/off oper - ation of the internal analog to digital converter. the eocb bit in the adcr register is used to indicate when the analog to digital conversion process is com - plete. this bit will be automatically set to 202 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request flag will be set in the interrupt control register, and if the inter - rupts are enabled, an appropriate internal interrupt sig - nal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d inter - nal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr register to check whether it has been cleared as an alternative method of detect - ing the end of an a/d conversion cycle. a d c s o u r c e f s y s / 3 , f s y s / 6 , f s y s / 8 , f s y s / 1 6 ? n a c s r r e g i s t e r a d c v r e f a / d r e f e r e n c e v o l t a g e a d r a / d d a t a r e g i s t e r s p c r 0 ~ p c r 3 a d c s 0 ~ a d c s 3 s t a r t e o c b a d c r r e g i s t e r p i n c o n f i g u r a t i o n b i t s c h a n n e l s e l e c t b i t s s t a r t b i t c l o c k d i v i d e r a t i o e n d o f c o n v e r s i o n b i t p c 0 / a n 8 ~ p c 7 / a n 1 5 p b 0 / a n 0 ~ p b 7 / a n 7 a/d converter structure a d c r r e g i s t e r s e l e c t a / d c h a n n e l b 7 b 0 s t a r t a c s 2 a c s 1 a c s 0 a c s 1 0 0 1 1 : : 1 a c s 2 0 0 0 0 : : 1 a c s 0 0 1 0 1 : : 1 : a n 0 : a n 1 : a n 2 : a n 3 : : : a n 1 5 e n d o f a / d c o n v e r s i o n f l a g 1 : n o t e n d o f a / d c o n v e r s i o n - a / d c o n v e r s i o n w a i t i n g o r i n p r o g r e s s 0 : e n d o f a / d c o n v e r s i o n - a / d c o n v e r s i o n e n d e d s t a r t t h e a / d c o n v e r s i o n 0 ? 1 ? 0 : s t a r t 0 ? 1 : r e s e t a / d c o n v e r t e r a n d s e t e o c b t o " 1 " e o c b a c s 3 a c s 3 0 0 0 0 : : 1 n o t i m p l e m e n t e d , r e a d a s " 0 " a/d converter control register
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 61 january 14, 2011 a/d converter clock source register - acsr the clock source for the a/d converter, which originates from the system clock f sys , is first divided by a division ratio, the value of which is determined by the adcs1 and adcs0 bits in the acsr register. the acsr control register also contains the pcr3~pcr0 bits which determine which pins on port b and port c are used as analog inputs for the a/d con- verter and which pins are to be used as normal i/o pins. if the 4-bit address on pcr3~pcr0 has a value of 2 1111 2 or higher, then all 16 pins, namely an0~ an15 will all be set as analog inputs. note that if the pcr3~pcr0 bits are all set to zero, then all the port b and port c pins will be setup as normal i/os and the internal a/d con - verter circuitry will be powered off to reduce the power consumption. although the a/d clock source is determined by the sys - tem clock f sys , and by bits adcs1 and adcs0, there are some limitations on the maximum a/d clock source speed that can be selected. as the minimum value of permissible a/d clock period, t ad , is 0.5 m s, care must be taken for sys - tem clock speeds in excess of 4mhz. for system clock speeds in excess of 4mhz, the adcs1 and adcs0 bits should not be set to 2 00 2 . doing so will give a/d clock peri - ods that are less than the minimum a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the de - vice, special care must be taken, as the values may be less than the specified minimum a/d clock period. a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on port b and port c. bits pcr3~pcr0 in the acsr register, not configuration options, determine whether the input pins are setup as normal port b and port c input/output pins or whether they are setup as an- alog inputs. in this way, pins can be changed under pro- gram control to change their function from normal i/o operation to analog inputs and vice versa. pull-high resis- tors, which are setup through configuration options, apply to the input pins only when they are used as normal i/o pins, if setup as a/d inputs the pull-high resistors will be automatically disconnected. note that it is not necessary to first setup the a/d pin as an input in the pbc or pcc port control register to enable the a/d input as when the pcr3~pcr0 bits enable an a/d input, the status of the port control register will be overridden. initialising the a/d converter the internal a/d converter must be initialised in a spe - cial way. each time the port b and port c a/d channel selection bits are modified by the program, the a/d con - verter must be re-initialised. if the a/d converter is not initialised after the channel selection bits are changed, the eocb flag may have an undefined value, which may produce a false end of conversion signal. to initialise the a/d converter after the channel selection bits have changed, then, within a time frame of one to ten instruc - tion cycles, the start bit in the adcr register must first be set high and then immediately cleared to zero. this will ensure that the eocb flag is correctly set to a high condition. a c s r r e g i s t e r s e l e c t a / d c o n v e r t e r c l o c k s o u r c e b 7 b 0 t e s t a d c s 1 a d c s 0 a d c s 1 0 0 1 1 a d c s 0 0 1 0 1 : s y s t e m c l o c k / 3 : s y s t e m c l o c k / 6 : s y s t e m c l o c k / 8 : s y s t e m c l o c k / 1 6 p b a n d p c a / d c h a n n e l c o n f i g u r a t i o n f o r t e s t m o d e u s e o n l y p c r 3 p c r 2 p c r 1 p c r 0 p c r 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 p c r 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 : p b a n d p c a / d c h a n n e l - a l l o f f : p b 0 a s a n 0 : p b 0 ~ p b 1 a s a n 0 ~ a n 1 : p b 0 ~ p b 2 a s a n 0 ~ a n 2 : p b 0 ~ p b 3 a s a n 0 ~ a n 3 : p b 0 ~ p b 4 a s a n 0 ~ a n 4 : p b 0 ~ p b 5 a s a n 0 ~ a n 5 : p b 0 ~ p b 6 a s a n 0 ~ a n 6 : p b 0 ~ p b 7 a s a n 0 ~ a n 7 : p b 0 ~ p b 7 , p c 0 a s a n 0 ~ a n 8 : p b 0 ~ p b 7 , p c 0 ~ p c 1 a s a n 0 ~ a n 9 : p b 0 ~ p b 7 , p c 0 ~ p c 2 a s a n 0 ~ a n 1 0 : p b 0 ~ p b 7 , p c 0 ~ p c 3 a s a n 0 ~ a n 1 1 : p b 0 ~ p b 7 , p c 0 ~ p c 4 a s a n 0 ~ a n 1 2 : p b 0 ~ p b 7 , p c 0 ~ p c 5 a s a n 0 ~ a n 1 3 : p b 0 ~ p b 7 , p c 0 ~ p c 7 a s a n 0 ~ a n 1 5 p c r 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 p c r 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 : d i s a b l e ( d e f a u l t ) 1 : e n a b l e a d o n a/d converter clock source register
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 62 january 14, 2011 summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d con - version process. step 1 select the required a/d conversion clock by correctly programming bits adcs1 and adcs0 in the acsr register. step 2 select which channel is to be connected to the internal a/d converter by correctly programming the acs3~ acs0 bits which are also contained in the adcr register. step 3 select which pins on port b and port c are to be used as a/d inputs and configure them as a/d input pins by correctly programming the pcr3~pcr0 bits in the acsr register. step 4 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interrupt control bit, emi, in the intc interrupt control register must be set to 212 and the a/d converter inter - rupt bit, eadi, in the intc register must also be set to 212. step 5 the analog to digital conversion process can now be initialised by setting the start bit in the adcr regis - ter from 202 to 212 and then to 202 again. note that this bit should have been originally set to 202. step 6 to check when the analog to digital conversion pro - cess is complete, the eocb bit in the adcr register can be polled. the conversion process is complete when this bit goes low. when this occurs the a/d data registers adr can be read to obtain the conversion value. as an alternative method if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr register is used, the interrupt enable step above can be omitted. the a/d conversion timing diagram shows graphically the various stages involved in an analog to digital con - version process and its associated timing. the setting up and operation of the a/d converter func - tion is fully under the control of the application program as there are no configuration options associated with the a/d converter. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can con- tinue with other functions. the time taken for the a/d conversion is 76t ad where t ad is equal to the a/d clock period. programming considerations when programming, special attention must be given to the a/d channel selection bits in the adsr register. if these bits are all cleared to zero no external pins will be selected for use as a/d input pins allowing the pins to be used as normal i/o pins. when this happens the power supplied to the internal a/d circuitry will be reduced re - sulting in a reduction of supply current. this ability to re - duce power by turning off the internal a/d function by clearing the a/d channel selection bits may be an impor - tant consideration in battery powered applications. another important programming consideration is that when the a/d channel selection bits change value, the a/d converter must be re-initialised. this is achieved by pulsing the start bit in the adcr register immediately after the channel selection bits have changed state. the exception to this is where the channel selection bits are all cleared, in which case the a/d converter is not re - quired to be re-initialised. 0 0 0 b 0 0 0 b 0 1 1 b 0 1 0 b s t a r t e o c b p c r 3 ~ p c r 0 a c s 3 ~ a c s 0 p o w e r - o n r e s e t e n d o f a / d c o n v e r s i o n 1 : d e f i n e p b , p c c o n f i g u r a t i o n 2 : s e l e c t a n a l o g c h a n n e l s t a r t o f a / d c o n v e r s i o n r e s e t a / d c o n v e r t e r 0 0 0 b s t a r t o f a / d c o n v e r s i o n r e s e t a / d c o n v e r t e r 0 0 0 b 1 . p o r t b a n d p o r t c s e t u p a s i / o s 2 . a / d c o n v e r t e r i s p o w e r e d o f f t o r e d u c e p o w e r c o n s u m p t i o n 1 0 0 b 0 0 1 b s t a r t o f a / d c o n v e r s i o n r e s e t a / d c o n v e r t e r d o n ' t c a r e e n d o f a / d c o n v e r s i o n e n d o f a / d c o n v e r s i o n s t a r t b i t s e t h i g h w i t h i n o n e t o t e n i n s t r u c t i o n c y c l e s a f t e r t h e p c r 0 ~ p c r 2 b i t s c h a n g e s t a t e a / d c l o c k m u s t b e f s y s / 3 , f s y s / 6 , f s y s / 8 , f s y s / 1 6 n o t e : a / d s a m p l i n g t i m e a / d s a m p l i n g t i m e a / d s a m p l i n g t i m e 3 2 t a d 3 2 t a d 3 2 t a d t a d c a / d c o n v e r s i o n t i m e a / d c o n v e r s i o n t i m e a / d c o n v e r s i o n t i m e t a d c t a d c a/d conversion timing
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 63 january 14, 2011 a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in the first exam - ple, the method of polling the eocb bit in the adcr register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr eadi ; disable adc interrupt mov a,00011001 mov acsr,a ; setup the acsr register to select fsys/6 as the a/d clock ; setup the acsr register to configure port pb0~pb2 as a/d ; inputs mov a,00000000 mov adcr,a ; setup the adcr register and select an0 to be connected to ; the a/d converter ; as the port b and port c channel bits have changed the ; following start signal (0 ?1? 0) must be issued within ; 10 instruction cycles : start_conversion: clr start set start ; reset a/d clr start ; start a/d polling_: sz eocb ; poll the adcr register eocb bit to detect end ; of a/d conversion jmp polling_eoc ; continue polling mov a,adr ; read conversion result value mov adrl_buffer,a ; save result to user defined register : jmp start_conversion ; start next a/d conversion example: using the interrupt method to detect the end of conversion clr eadi ; disable adc interrupt mov a,00011001b mov acsr,a ; setup the acsr register to select fsys/6 as the a/d clock mov a,00000000b ; setup adcr register to configure port pb0~pb2 ; as a/d inputs mov adcr,a ; and select an0 to be connected to the a/d : ; as the port b channel bits have changed the ; following start signal(0 ?1? 0) must be issued ; within 10 instruction cycles : start_conversion: clr start set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request flag set eadi ; enable adc interrupt set emi ; enable global interrupt : : : ; adc interrupt service routine adc_: mov acc_stack,a ; save acc to user defined memory a,status mov status_stack,a ; save status to user defined memory : : mov a,adr ; read conversion result value mov adrl_buffer,a ; save result to user defined register : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defined memory mov a,acc_stack ; restore acc from user defined memory
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 64 january 14, 2011 f f e h ( ) a / d c o n v e r s i o n r e s u l t f f f h f f d h 0 3 h 0 2 h 0 1 h 0 . 5 l s b 0 1 2 3 4 0 9 3 4 0 9 4 4 0 9 5 4 0 9 6 a n a l o g i n p u t v o l t a g e 1 . 5 l s b v d d 4 0 9 6 ideal a/d transfer function a/d transfer function as the device contain a 12-bit a/d converter, its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the vdd voltage, this gives a single bit analog input value of v dd /4096. the diagram show the ideal transfer function between the analog input value and the digitised output value for the a/d converter. note that to reduce the quantisation error, a 2.5 lsb off - set is added to the a/d converter input. except for the digitised zero value, the subsequent digitised values will change at a point 2.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 2.5 lsb below the v dd level. spi serial interface the device includes two spi serial interfaces. the spi interface is a full duplex serial data link, originally de - signed by motorola, which allows multiple devices con - nected to the same spi bus to communicate with each other. the devices communicate using a master/slave technique where only the single master device can initi - ate a data transfer. a simple four line signal bus is used for all communication. spi interface communication four lines are used for each spi function. these are, sdia/b - serial data input, sdoa/b - serial data out - put, sclka/b - serial clock and scsa/b - slave select. note that the condition of the slave select line is condi - tioned by the csena/b bit in the sbcra/b control reg - ister. if the csena/b bit is high then the scsa/b line is active while if the bit is low then the scsa/b line will be in a floating condition. the accompanying timing dia - gram depicts the basic timing protocol of the spi bus. spi registers there are two registers for control of the spi interface. these are the sbcra/b register which is the control register and the sbdra/b which is the data register. the sbcra/b register is used to setup the required setup parameters for the spi bus and also used to store associated operating flags, while the sbdra/b register is used for data storage. after power on, the contents of the sbdra/b register will be in an unknown condition while the sbcra/b reg - ister will default to the condition below: cksn m1n m0n sbenn mlsn csenn wcoln trfn 0 1 1 0 0 0 0 0 note: 2n2 where n=a~b note that data written to the sbdra/b register will only be written to the txrx buffer, whereas data read from the sbdra/b register will actual be read from the register. spi bus enable/disable to enable the spi bus, the sbena/b bit should be set high, then the sclka/b, sdia/b, sdoa/b and scsa/b lines should all be zero, then wait for data to be written to the sbdra/b (txrx buffer) register. for the master mode, after data has been written to the sbdra/b (txrx buffer) register then transmission or reception will start automatically. when all the data has been transferred, the trfa/b bit should be set. for the slave mode, when clock pulses are received on sclka/b, data in the txrx buffer will be shifted out or data on sdia/b will be shifted in. to disable the spi bus sclka/b, sdia/b, sdoa/b, scsa/b should be floating.
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 65 january 14, 2011 spi operation all communication is carried out using the 4-line inter - face for both master or slave mode. the timing diagram shows the basic operation of the bus. the csena/b bit in the sbcra/b register controls the overall function of the spi interface. setting this bit high, will enable the spi interface by allowing the scsa/b line to be active, which can then be used to control the spi in - terface. if the csena/b bit is low, the spi interface will be disabled and the scsa/b line will be in a floating condi - tion and can therefore not be used for control of the spi interface. the sbena/b bit in the sbcra/b register must also be high which will place the sdia/b line in a floating condition and the sdoa/b line high. if in the mas - ter mode the sclka/b line will be either high or low de - pending upon the clock polarity configuration option. if in the slave mode the sclka/b line will be in a floating con - dition. if sbena/b is low then the bus will be disabled and scsa/b , sdia/b, sdoa/b and sclka/b will all be in a floating condition. in the master mode, the master will always generate the clock signal. the clock and data transmission will be ini - tiated after data has been written to the sbdra/b regis - ter. in the slave mode, the clock signal will be received from an external master device for both data transmis - sion or reception. the following sequences show the or - der to be followed for data transfer in both master and slave mode: master mode step 1. select the clock source using the cksa/b bit in the sbcra/b control register step 2. setup the m0a/b and m1a/b bits in the sbcra/b control register to select the master mode and the required baud rate. values of 00, 01 or 10 can be selected. step 3. setup the csena/b bit and setup the mlsa/b bit to choose if the data is msb or lsb first, this must be same as the slave device. step 4. setup the sbena/b bit in the sbcra/b control register to enable the spi interface. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s b d r ( r e c e i v e d d a t a r e g i s t e r ) m u x s d o b u f f e r m u x m l s d a t a b u s m u x m a s t e r o r s l a v e s d i a / b s d o a / b i n t e r n a l b a u d r a t e c l o c k s c k a / b c l o c k p o l a r i t y c 2c 1c 0 s b e n a / b i n t e r n a l b u s y f l a g s b e n a / b w r i t e s b d r a / b w c o l a / b f l a g t r f a / b a n d , s t a r t s b e n a / b e n a n d w r i t e s b d r a / b w r i t e s b d r a / b e n a b l e / d i s a b l e s c s a / b e n m a s t e r o r s l a v e c s e n a / b s b e n a / b a n d , s t a r t a n d , s t a r t spi block diagram note: wcola/b: set by spi cleared by users csena/b: enable/disable chip selection function pin master mode: 1/0 = with/without scsa/b output function slave mode: 1/0 = with/without scsa/b input control function sbena/b: enable/disable serial bus (0: initialise all status flags) when sbena/b=0, all status flags should be initialised when sbena/b=1, all spi related function pins should stay at floating state trfa/b: 1 = data transmitted or received, 0= data is transmitting or still not received cpol: i/o = clock polarity rising/falling edge : mask option if clock polarity set to rising edge (spia_cpol/spib_cpol=1), serial clock timing follow clk , otherwise (spia_cpol/spib_cpol=0) clk is the serial clock timing.
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 66 january 14, 2011 step 5. for write operations: write the data to the sbdra/b register, which will actually place the data into the txrx buffer. then use the sclka/b and scsa/b lines to output the data. goto to step 6.for read operations: the data transferred in on the sdia/b line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the sbdra/b register. step 6. check the wcola/b bit, if set high then a collision error has occurred so return to step5. if equal to zero then go to the following step. step 7. check the trfa/b bit or wait for an spi serial bus interrupt. step 8. read data from the sbdra/b register. step 9. clear trfa/b. step10. goto step 5. slave mode: step 1. the cksa/b bit has a don t care value in the slave mode. step 2. setup the m0a/b and m1a/b bits to 00 to select the slave mode. the cksa/b bit is dont care. step 3. setup the csena/b bit and setup the mlsa/b bit to choose if the data is msb or lsb first, this must be same as the master device. step 4. setup the sbena/b bit in the sbcra/b control register to enable the spi interface. step 5. for write operations: write data to the sbcra/b register, which will actually place the data into the txrx register, then wait for the master clock and scsa/b signal. after this goto step 6. for read operations: the data transferred in on the sdia/b line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the sbdra/b register. step 6. check the wcola/b bit, if set high then a collision error has occurred so return to step5. if equal to zero then goto the following step. step 7. check the trfa/b bit or wait for an spi serial bus interrupt. step 8. read data from the sbdra/b register. step 9. clear trfa/b step10. step 5 spi configuration options and status control one option is to enable the operation of the wcola/b, write collision bit, in the sbcra/b register. some control in spir register. the spia_cpol/ spib_cpol select the clock polarity of the sck line. the spia_mode/ spib_mode select spi data output mode. spi include four pins , can share i/o mode status . the status control combine with four bits for spi and sbcra/b register. include spia_csen/spib_csen, spia_io/spib_io for spi register and csena/b, sbena/b for sbcra/b register. control bit for register spi share function pins status spin_io spin_csen sbenn csenn scsn sckn sdon sdin 0 x x x i/o mode i/o mode i/o mode i/o mode 1 0 0 x i/o mode i/o mode i/o mode i/o mode 1 0 1 x i/o mode spi mode spi mode spi mode(z) 1 1 0 x i/o mode i/o mode i/o mode i/o mode 1 1 1 0 spi mode (z) spi mode spi mode spi mode(z) 1 1 1 1 spi mode spi mode spi mode spi mode(z) note: 2n2 where n=a~b x: dont care (z) floating
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 67 january 14, 2011 p a 3 / s d o a , p b 3 / s d o b p a 2 / s d i a , p b 2 / s d i b p a 1 / s c l k a , p b 1 / s c l k b ( s p i a _ c p o l / s p i b _ c p o l = 0 ) p a 1 / s c l k a , p b 1 / s c l k b ( s p i a _ c p o l / s p i b _ c p o l = 1 ) s p i _ m o d e = 0 s p i _ m o d e = 1 p a 2 / s d i a , p b 2 / s d i b p a 3 / s d o a , p b 3 / s d o b p a 1 / s c l k a , p b 1 / s c l k b ( s p i a _ c p o l / s p i b _ c p o l = 1 ) p a 0 / s c s a , p b 0 / s c s b ( s p i a _ c s e n / s p i b _ c s e n = 1 ) p a 0 / s c s a , p b 0 / s c s b ( s p i a _ c s e n / s p i b _ c s e n = 1 ) p a 1 / s c l k a , p b 1 / s c l k b ( s p i a _ c p o l / s p i b _ c p o l = 0 ) s b c r n d e f a u l t s b d r n d e f a u l t n o t e : c k s n m 1 n m 0 n s b e n n m l s n c s e n n w c o l n t r f n d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 u u u u u u u u s b c r n : s e r i a l b u s c o n t r o l r e g i s t e r s b d r n : s s e r i a l b u s d a t a r e g i s t e r " n " w h e r e n = a ~ b " u " m e a n s u n c h a n g e d . d 7 / d 0 d 6 / d 1 d 5 / d 2 d 4 / d 3 d 3 / d 4 d 2 / d 5 d 1 / d 6 d 0 / d 7 d 7 / d 0 d 6 / d 1 d 5 / d 2 d 4 / d 3 d 3 / d 4 d 2 / d 5 d 1 / d 6 d 0 / d 7 d 7 / d 0 d 6 / d 1 d 5 / d 2 d 4 / d 3 d 3 / d 4 d 2 / d 5 d 1 / d 6 d 0 / d 7 d 7 / d 0 d 6 / d 1 d 5 / d 2 d 4 / d 3 d 3 / d 4 d 2 / d 5 d 1 / d 6 d 0 / d 7 s b e n a / b = c s e n a / b = 1 a n d w r i t e d a t a t o s b d r a / b s b e n a / b = 1 , c s e n a / b = 0 a n d w r i t e d a t a t o s b d r a / b ( i f p u l l - h i g h e d ) s b e n a / b = c s e n a / b = 1 a n d w r i t e d a t a t o s b d r a / b s b e n a / b = 1 , c s e n a / b = 0 a n d w r i t e d a t a t o s b d r a / b ( i f p u l l - h i g h e d ) spi bus timing
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 68 january 14, 2011 error detection the wcola/b bit in the sbcra/b register is provided to indicate errors during data transfer. the bit is set by the serial interface but must be cleared by the applica - tion program. this bit indicates a data collision has oc - curred which happens if a write to the sbdra/b register takes place during a data transfer operation and will pre - vent the write operation from continuing. the bit will be set high by the serial interface but has to be cleared by the user application program. the overall function of the wcola/b bit can be disabled or enabled by a configu - ration option. s b c r a / s b c r b r e g i s t e r b 7 b 0 c k s m 1 m 0 s b e n m l s c s e n w c o l t r f t r a n s m i t t / r e c e i v e f l a g 0 : n o t c o m p l e t e 1 : t r a n s m i s s i o n / r e c e p t i o n c o m p l e t e w r i t e c o l l i s i o n b i t 0 : c o l l i s i o n f r e e 1 : c o l l i s i o n d e t e c t e d s e l e c t i o n s i g n a l e n a b l e / d i s a b l e b i t 0 : s c s a / s c s b f l o a t i n g 1 : e n a b l e m s b / l s b f i r s t b i t 0 : l s b s h i f t f i r s t 1 : m s b s h i f t f i r s t s e r i a l b u s e n a b l e / d i s a b l e b i t 0 : d i s a b l e 1 : e n a b l e d e p e n d e n t u p o n c s e n a / c s e n b b i t m a s t e r / s l a v e / b a u d r a t e b i t s m a s t e r , b a u d r a t e : f s i o m a s t e r , b a u d r a t e : f s i o / 4 m a s t e r , b a u d r a t e : f s i o / 1 6 s l a v e m o d e m 1 0 0 1 1 m 0 0 1 0 1 c l o c k s o u r c e s e l e c t b i t 0 : f s i o = f s y s / 4 1 : f s i o = f s y s spi interface control register
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 69 january 14, 2011 programming considerations when the device is placed into the power down mode note that data reception and transmission will continue. the trfa/b bit is used to generate an interrupt when the data has been transferred or received. spi transfer control flowchart s p i a _ i o = 1 o r s p i b _ i o = 1 w r i t e d a t a i n t o s b d r a / b w c o l a / b = 1 ? c l e a r w c o l a / b y e s n o r e a d d a t a f r o m s b d r a / b c l e a r t r f a / b t r a n s f e r f i n i s h e d ? e n d m a s t e r o r s l a v e m a s t e r s l a v e a a s i m [ 2 : 0 ] = 1 0 1 s p i t r a n s f e r s i m [ 2 : 0 ] = 0 0 0 , 0 0 1 , 0 1 0 , 0 1 1 o r 1 0 0 c o n f i g u r e c s e n a / b a n d m l s t r a n s m i s s i o n c o m p l e t e d ? ( t r f a / b = 1 ? ) y e s y e s n o n o
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 70 january 14, 2011 bit no. label function 0 spia_io 1: io, 0: spi (default) 1 spia_mode 1: spi first output the data immediately after the spi is enable. and spi output the data in the falling edge (polarity=1) or rising edge (polarity=0); spi read data in the in the ris - ing edge (polarity=1) or falling edge (polarity=0) 0: spi output the data in the rising edge (polarity=1) or falling edge (polarity=0); spi read data in the in the falling edge (polarity=1) or rising edge (polarity=0); (default) 2 spia_cpol 1: clock polarity rising 0: clock polarity falling (default falling) 3 spia_csen 1: spi_csen: enable , this bit is used to enable/disable software csen function (default enable) 0: spi_csen disable, scsa define as gpio 4 spib_io 1: io, 0: spi (default) 5 spib_mode 1: spi first output the data immediately after the spi is enable. and spi output the data in the falling edge (polarity=1) or rising edge (polarity=0); spi read data in the in the ris - ing edge (polarity=1) or falling edge (polarity=0) 0: spi output the data in the rising edge (polarity=1) or falling edge (polarity=0); spi read data in the in the falling edge (polarity=1) or rising edge (polarity=0); (default) 6 spib_cpol 1: clock polarity rising 0: clock polarity falling (default falling) 7 spib_csen 1: spi_csen: enable, this bit is used to enable/disable software csen function (default enable) 0: spi_csen disable, scsb define as gpio spi register usb interface the device includes a usb interface function allowing for the convenient design of usb peripheral products. the usb disable/enable control bit 2usbdis2 is in the pwmctl register. if the usb is disabled, then v33o and the d+/d- lines will be floating and the usb sie will be disabled. power plane there are four power planes for the device: usb sie vdd, vddio and the mcu vdd and flash memory power for the ht82a6208/ht82a6216. for the usb sie vdd will supply all circuits related to the usb sie and be sourced from pin 2ubus2 . once the usb is re - moved from the usb and there is no power in the usb bus, the usb sie circuit is no longer operational. for the pb port, it can be configured using a configuration option to define the if the pins pb0~pb7 are supplied by either the mcu vdd, or if pins pb0~pb6 are supplied by the power pin vddio, in which case power will be supplied on pin pb7. in the lat - ter configuration, pb7 will be configured as a power pin vddio and not a normal i/o pin. for the mcu vdd, it supplies all the ht82a623r circuit except the usb sie which is supply by ubus. for the ht82a6208 and ht82a6216 the internal flash memory is supplied by vcc. usb suspend wake-up remote wake-up if there is no signal on the usb bus for over 3ms, the de- vice will enter a suspend mode. the suspend flag, susp, in the usc register, will then be set high and a usb interrupt will be generated to indicate that the de- vice should jump to the suspend state to meet the re - quirements of the usb suspend current spec. in order to meet the requirements of the suspend current, the firm - ware should disable the usb clock by clearing the usbcken bit to zero. the suspend current can be further decreased by set - ting the susp2 bit in the ucc register. when the re - sume signal is sent out by the host, the device will be woken up the by the usb interrupt and the resume bit in the usc register will be set. to ensure correct device operation, the program must set the usbcken bit in the ucc register high and clear the susp2 bit in the ucc register. the resume signal will be cleared before the idle signal is sent out by the host and the suspend line in the usc register will change to zero. so when the mcu s u s p e n d u s b r e s u m e s i g n a l u s b _ i n t
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 71 january 14, 2011 detects the suspend bit in the usc register, the condi - tion of the resume line should be noted and taken into consideration. the device has a remote wake up function which can wake-up the usb host by sending a wake-up pulse through rmwk in the usc register. once the usb host receives a wake-up signal from the device it will send a resume signal to the device. usb interface operation the device has 8 endpoints, ep0~ep3. ep0 supports control transfer. all ep1~ep3 support interrupt or bulk transfer. all endpoints except ep0 can be configured as 8, 16, 32 or 64 fifo size using the register ufc0 and ufc1. ep0 has an 8-byte fifo size. the total fifo size is 64+8 bytes. the urd in the usc register is the usb reset signal control function definition bit. bit no. label function 0 esd this bit will set to 212 when there are esd issue. this bit is set by sie and clear by f/w. 1 pub bit3=1, d+, and d- have a 500kw pull-high bit3=0, no pull-high (default on mcu reset) 2 se0 this bit is used to indicate the sie has detect a se0 noise in the usb bus. this bit is set by sie and clear by f/w. 3 se1 this bit is used to indicate the sie has detect a se1 noise in the usb bus. this bit is set by sie and clear by f/w. 4 ps2/ dai usbd-/data input. 5 ps2/ cki usbd+/clk input. 6 ps2/ dao output for driving usbd-/data pin, when work under 3d ps2 mouse function. default value is 212. 7 ps2/ cko output for driving usbd+/clk pin, when work under 3d ps2 mouse function. default value is 212. usb_stat register bit no. label function 0 ep0en control the usb endpoint0 interrupt (1=enabled; 0=disabled) 1 ep1en control the usb endpoint1 interrupt (1=enabled; 0=disabled) 2 ep2en control the usb endpoint2 interrupt (1=enabled; 0=disabled) 3 ep3en control the usb endpoint3 interrupt (1=enabled; 0=disabled) 4~7 ? unused bit, read as 202 uint1 register s u s p e n d u s b r e s u m e s i g n a l u s b _ i n t r m w k m i n . 1 u s b c l k m i n . 2 . 5 m s
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 72 january 14, 2011 bit no. label function 0 susp read only, usb suspend indication. when this bit is set to 212 (set by sie), it indicates that the usb bus has entered the suspend mode. the usb interrupt is also triggered when this bit changes from low to high. 1 rmwk usb remote wake-up command. it is set by mcu to leave the usb host leaving the suspend mode. 2 urst usb reset indication. this bit is set/cleared by the usb sie. this bit is used to detect a usb reset event on the usb bus. when this bit is set to 212 , this indicates that a usb reset has occurred and that a usb interrupt will be initialized. 3 resume usb resume indication. when the usb leaves the suspend mode, this bit is set to 212 (set by sie). when the resume is set by sie, an interrupt will be generated to wake-up the mcu. in order to detect the suspend state, the mcu should set usbcken and clear susp2 (in the ucc register) to enable the sie detect function. resume will be cleared when the susp goes to 202 . when the mcu is detecting the susp, the condition of re - sume (causes the mcu to wake-up) should be noted and taken into consideration. 4 v33o 0/1: turn-off/on v33o output. 5 pll 0: turn-on pll (default), 1: turn off pll. 6 selps2 when set to 1, indicated the chip work under ps2 mode. default value is 202. 7 urd usb reset signal control function definition. 1: usb reset signal will reset mcu. 0: usb reset signal cannot reset mcu. usc register the usr register which is the endpoint interrupt status register, is used to indicate which endpoint is accessed and to select the usb bus. the endpoint request flags, ep0f, ep1f, ep2f and ep3f, are used to indicate which endpoints are accessed. if an endpoint is accessed, the related endpoint request flag will be set high and a usb interrupt will be generated, if the usb interrupt is enabled and the stack is not full. when the active endpoint request flag is serviced, the endpoint request flag has to be cleared to zero using the program. bit no. label function 0 ep0f when this bit is set to 212 (set by sie), it indicates that endpoint 0 has been accessed and a usb interrupt will occur. when the interrupt has been serviced, this bit should be cleared by software. 1 ep1f when this bit is set to 212 (set by sie), it indicates that endpoint 1 has been accessed and a usb interrupt will occur. when the interrupt has been serviced, this bit should be cleared by software. 2 ep2f when this bit is set to 212 (set by sie), it indicates that endpoint 2 has been accessed and a usb interrupt will occur. when the interrupt has been serviced, this bit should be cleared by software. 3 ep3f when this bit is set to 212 (set by sie), it indicates that endpoint 3 has been accessed and a usb interrupt will occur. when the interrupt has been serviced, this bit should be cleared by software. 4~7 ? unused bit, read as 202 usr register
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 73 january 14, 2011 there is a system clock control register to select the clock used in the mcu. this register consists of a usb clock con - trol bit, usbcken, a second suspend mode control bit, susp2, and a system clock selection bit, sysclk. the endpoint selection is determined by eps2, eps1 and eps0. bit no. label function 0 1 2 eps0 eps1 eps2 accessing endpoint fifo selection. eps2, eps1, eps0: 000: select endpoint 0 fifo (control) 001: select endpoint 1 fifo 010: select endpoint 2 fifo 011: select endpoint 3 fifo if the selected endpoints do not exist, the related functions will be absent. 3 usbcken usb clock control bit. when this bit is set to 212 , it indicates that the usb clock is en - abled. otherwise, the usb clock is turned-off. 4 susp2 this bit is used for reducing power consumption in suspend mode. in normal mode, clean this bit to 202. in halt mode, set this bit to 212 for reducing power consumption. 5 fsys16mhz this bit is used to define if the mcu system clock comes form an external osc or comes from the pll output 16mhz clock. 0: system clock sourced from osc. 1: system clock sourced from the pll output 16mhz. 6 sysclk this bit is used to specify the mcu system clock oscillator frequency. for a 6mhz crystal oscillator or resonator, set this bit to 212. for a 12mhz crystal oscillator or resonator, clear this bit to 202. 7 rctrl this bit is used to control whether there is 7.5kw resistor between d+ and vbus. 0: no 7.5kw between d+ and vbus (default) 1: has 7.5kw between d+ and vbus ucc register the awr register contains the current address and a remote wake up function control bit. the initial value of awr is 200h2 . the address value extracted from the usb command has not to be loaded into this register until the setup stage has finished. bit no. label function 0 wken usb remote-wake-up enable/disable (1/0) 1~7 ad0~ad6 usb device address awr register the stall register shows if the corresponding endpoint has worked properly or not. as soon as endpoint improper op - eration occurs, the related bit in the stall register has to be set high. the stall register bits will be cleared by a usb reset signal and a setup token event. bit no. label function 0~3 stl0~ stl3 set by the users when related usb endpoints were stalled. cleared by a usb reset. the stl0 is also cleared by a setup token event. 4~7 ? unused bit, read as 202 stall register
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 74 january 14, 2011 the sies register is only used for ep0 except for the nmi bit, which can control all endpoints bit no. label function 0 aset this bit is used to configure the sie to automatically change the device address by the value stored in the awr register. when this bit is set to 212 by firmware, the sie will update the device address by the value stored in the awr register after the pc host has success - fully read the data from he device by an in operation. otherwise, when this bit is cleared to 202 , the sie will update the device address immediately after an address is written to the awr register. so, in order to work properly, the firmware has to clear this bit after a next valid setup token is received. 1 err this bit is used to indicate that some errors have occurred when the fifo is accessed. this bit is set by sie and should be cleared by firmware. this bit is used for all endpoint 2 out this bit is used to indicate the out token (except the out zero length token) has been re - ceived. the firmware clears this bit after the out data has been read. also, this bit will be cleared by sie after the next valid setup token is received. 3 in this bit is used to indicate the current usb receiving signal from pc host is in token. 4 no ack this bit will set to 212 once sie discover ther are some error condition so the sie is not re - sponse (nak or ack or data) for the usb token. this bit is set by sie and clear by f/w. 5 ? unused bit, read as 202 6 crcf this bit will set to 212 when there are the following three condition is happened: crc error, pid error, bit stuffing error. this bit is set by sie and clear by f/w. 7 nmi nak token interrupt mask flag. if this bit set, when the device sent a nak token to the host, an interrupt will be disabled. otherwise if this bit is cleared, when the device sends a nak token to the host, it will enter the interrupt sub-routine. this bit is used for all endpoint. sies register the misc register combines command and status to control the desired endpoint fifo action and to show the status of the desired endpoint fifo. misc will be cleared by a usb reset signal. bit no. label function 0 request after setting the status of the desired one, fifo can be requested by setting this bit high. after finishing, this bit must be set low. 1 tx to represent the direction and transition end mcu access. when set to logic 1, the mcu desires to write data to the fifo. after finishing, this bit must be set to logic 0 before termi - nating request to represent transition end. for an mcu read operation, this bit must be set to logic 0 and set to logic 1 after finishing. 2 clear mcu requests to clear the fifo, even if the fifo is not ready. after clearing the fifo, the usb interface will send force_tx_err to tell the host that data under-run if the host wants to read data. 3~4 ? unused bit, read as 202 5 setcmd to show that the data in the fifo is a setup command. this bit is set by hardware and clear by firmware. 6 ready to show that the desired fifo is ready. 7 len0 to show that the host sent a 0-sized packet to the mcu. this bit must be cleared by a read action to the corresponding fifo. misc register
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 75 january 14, 2011 bit no. label function 0 fifo_def once this bit set to 212 by firmware, the sie should redefine the fifo configuration. this bit is automatically cleared by sie 1 seti1* input fifo for ep1 eanble 1/disable 0; default disable 2 seti2* input fifo for ep2 eanble 1/disable 0; default disable 3 seti3* input fifo for ep3 eanble 1/disable 0; default disable 4~7 ? unused bit, read as 202 note: 2*2 it is only required to set the data pipe as an input pipe or output pipe. the purpose of this function is to avoid the host sending an abnormal in or out token and disabling the endpoint. ufien register, usb endpoint 1~endpoint 3 set in pipe enable register bit no. label function 0 ? unused bit, read as 202 1 seto1** output fifo for ep1 eanble 1/disable 0; default disable 2 seto2** output fifo for ep2 eanble 1/disable 0; default disable 3 seto3** output fifo for ep3 eanble 1/disable 0; default disable 4~7 ? unused bit, read as 202 note: 2*2 usb definition: when the host sends a 2 set configuration2 , the data pipe should send the data0 (about the data toggle) first. so, when the device receives a 2 set configuration2 setup command, the user needs to toggle this bit as the following data will send a data0 first. 2**2 it is only required to set the data pipe as an input pipe or output pipe. the purpose of this function is to avoid the host sending a abnormal in or out token and disabling the endpoint. ufoen register, usb endpoint 1~endpoint 3 set out pipe enable register bit no. label function 0 1 ram_def0 ram_def1 00: ram0 input fifo, ram1 output fifo 01: both ram0 and ram1 are output fifo 10: both ram0 and ram1 are input fifo 11: ram0 output fifo, ram1 input fifo 2 3 e1fs0 e1fs1 define endpoint 1 fifo size e1fs1, e1fs0: 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte 4 5 e2fs0 e2fs1 define endpoint 2 fifo size e2fs1, e2fs0: 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte 6 7 e3fs0 e3fs1 define endpoint 3 fifo size e3fs1, e3fs0: 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte ufc0 usb fifo size control register 0
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 76 january 14, 2011 the total fifo size is 64+8 bytes. all endpoints except ep0 can be defined by registers ufoen, ufien, ufc0 and ufc. there are three fifo mapped as follow: 8 bytes fifo for endpoint0 ram0 fifo for other input endpoint (1~3) ram1 fifo for other output endpoint (1~3) bit no. label function 0~3 fifo0~ fifo3 epi accessing register (i=0~3). when an endpoint is disabled, the corresponding accessing register should be disabled. 4~7 ? unused bit, read as 202 fifo0~fifo3 usb endpoint accessing registers definitions configuration options no. options 1 pa pull-high enable/disable (1/0) (default: enable) 2 pb pull-high enable/disable (1/0) by nibble (default: enable) 3 pc pull-high enable/disable (1/0) by nibble (default: enable) 4 pc, wake-up enable/disable (1/0) by nibble (default: disable) 5 spia wcol: enable/disable (default disable) 6 built-in 1.5k (default no built-in) 7 has 7.5kw resistor enable bit (default no) 8 tbhp enable or disable (default disable) 9 low voltage reset: enable/disable (default: enable) 10 wdt enable/disable (0/1) (default: enable) 11 wdt clock source: f sys /4 or rc (default t1) 12 clr wdt instructions: one or two clear wdt instruction(s) (0/1) (default: 1 inst.) 13 pa nmos or cmos output type (default cmos) 14 port a wake-up enable/disable (1/0) by bit (default: enable) 15 pb0~pb3 nmos or cmos output type (default cmos) 16 port b wake-up enable/disable (1/0) by bit (default: disable) 17 0: pb7 used as gpio 1: pb7 used as vddio pin 18 0: pb0~pb6 use power=v dd 1: pb0~pb6 use power=v ddio 19 pd nmos or cmos output type (default cmos) 20 pd pull-high enable/disable (1/0) by nibble (default: enable) 21 pd, wake-up enable/disable (1/0) by nibble (default: disable) 22 spib wcol: enable/disable (default disable)
application circuits crystal or ceramic resonator for multiple i/o applications note: the resistance and capacitance for the reset circuit should be designed in such a way as to ensure that vdd is stable and remains within a valid operating voltage range before bringing res high. x1 can be 6mhz or 12mhz, and should be located as close to the osc1/osc2 pins as possible. * these capacitors should be placed close to the usb connector. ** this capacitor should be placed close to the mcu. ht82a623r/ht82a6208/ht82a6216 rev. 1.30 77 january 14, 2011 u s b d + / c l k u s b d - / d a t a v 3 3 o 1 . 5 k w v d d u s b - u s b + v s s 3 3 w 3 3 w p a 0 ~ p a 7 p b 0 ~ p b 7 p c 0 ~ p c 7 p d 0 ~ p d 7 0 . 1 m f 0 . 1 m f * v d d o s c 1 o s c 2 r e s v s s 0 . 1 m f 1 0 0 k w 1 0 m f * x 1 0 . 1 m f * *
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 78 january 14, 2011 instruction set introduction c e n t r a l t o t h e s u c c e s s f u l o p e r a t i o n o f a n y microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 m s and branch or call instructions would be im - plemented within 1 m s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc - tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple - ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be 2 clr pcl2 or 2 mov pcl, a2 . for the case of skip instructions, it must be noted that if the re - sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 79 january 14, 2011 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the 2set [m].i2 or 2 clr [m].i2 instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the 2 halt2 in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 80 january 14, 2011 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the 2 clr wdt12 and 2 clr wdt22 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both 2 clr wdt12 and 2 clr wdt22 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc ? acc + [m] + c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] ? acc + [m] + c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc ? acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc ? acc + x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] ? acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc ? acc 2and2 [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc ? acc 2and2 x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] ? acc 2and2 [m] affected flag(s) z ht82a623r/ht82a6208/ht82a6216 rev. 1.30 81 january 14, 2011
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack ? program counter + 1 program counter ? addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] ? 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i ? 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to ? 0 pdf ? 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to ? 0 pdf ? 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to ? 0 pdf ? 0 affected flag(s) to, pdf ht82a623r/ht82a6208/ht82a6216 rev. 1.30 82 january 14, 2011
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] ? [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc ? [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] ? acc + 00h or [m] ? acc + 06h or [m] ? acc + 60h or [m] ? acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] ? [m] - 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc ? [m] - 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to ? 0 pdf ? 1 affected flag(s) to, pdf ht82a623r/ht82a6208/ht82a6216 rev. 1.30 83 january 14, 2011
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] ? [m] + 1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc ? [m] + 1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter ? addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc ? [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc ? x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] ? acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc ? acc 2or2 [m] affected flag(s) z ht82a623r/ht82a6208/ht82a6216 rev. 1.30 84 january 14, 2011
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc ? acc 2or2 x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] ? acc 2or2 [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter ? stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter ? stack acc ? x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter ? stack emi ? 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) ? [m].i; (i = 0~6) [m].0 ? [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) ? [m].i; (i = 0~6) acc.0 ? [m].7 affected flag(s) none ht82a623r/ht82a6208/ht82a6216 rev. 1.30 85 january 14, 2011
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) ? [m].i; (i = 0~6) [m].0 ? c c ? [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) ? [m].i; (i = 0~6) acc.0 ? c c ? [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i ? [m].(i+1); (i = 0~6) [m].7 ? [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i ? [m].(i+1); (i = 0~6) acc.7 ? [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i ? [m].(i+1); (i = 0~6) [m].7 ? c c ? [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i ? [m].(i+1); (i = 0~6) acc.7 ? c c ? [m].0 affected flag(s) c ht82a623r/ht82a6208/ht82a6216 rev. 1.30 86 january 14, 2011
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc ? acc - [m] - c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] ? acc - [m] - c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] ? [m] - 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc ? [m] - 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ? ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i ? 1 affected flag(s) none ht82a623r/ht82a6208/ht82a6216 rev. 1.30 87 january 14, 2011
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] ? [m] + 1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc ? [m] + 1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 1 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc ? acc - [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] ? acc - [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc ? acc - x affected flag(s) ov, z, ac, c ht82a623r/ht82a6208/ht82a6216 rev. 1.30 88 january 14, 2011
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 ? [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 ? [m].7 ~ [m].4 acc.7 ~ acc.4 ? [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc ? [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] ? program code (low byte) tblh ? program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] ? program code (low byte) tblh ? program code (high byte) affected flag(s) none ht82a623r/ht82a6208/ht82a6216 rev. 1.30 89 january 14, 2011
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc ? acc 2xor2 [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] ? acc 2xor2 [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc ? acc 2xor2 x affected flag(s) z ht82a623r/ht82a6208/ht82a6216 rev. 1.30 90 january 14, 2011
package information 28-pin sop (300mil) outline dimensions ms-013ms-013 symbol dimensions in inch min. nom. max. a 0.393 ? 0.419 b 0.256 ? 0.300 c 0.012 ? 0.020 c 0.697 ? 0.713 d ? ? 0.104 e ? 0.050 ? f 0.004 ? 0.012 g 0.016 ? 0.050 h 0.008 ? 0.013 a 0 ? 8 symbol dimensions in mm min. nom. max. a 9.98 ? 10.64 b 6.50 ? 7.62 c 0.30 ? 0.51 c 17.70 ? 18.11 d ? ? 2.64 e ? 1.27 ? f 0.10 ? 0.30 g 0.41 ? 1.27 h 0.20 ? 0.33 a 0 ? 8 ht82a623r/ht82a6208/ht82a6216 rev. 1.30 91 january 14, 2011 2 8 1 1 5 1 4 a b c d f c ' g h a e
28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 ? 0.244 b 0.150 ? 0.157 c 0.008 ? 0.012 c 0.386 ? 0.394 d 0.054 ? 0.060 e ? 0.025 ? f 0.004 ? 0.010 g 0.022 ? 0.028 h 0.007 ? 0.010 a 0 ? 8 symbol dimensions in mm min. nom. max. a 5.79 ? 6.20 b 3.81 ? 3.99 c 0.20 ? 0.30 c 9.80 ? 10.01 d 1.37 ? 1.52 e ? 0.64 ? f 0.10 ? 0.25 g 0.56 ? 0.71 h 0.18 ? 0.25 a 0 ? 8 ht82a623r/ht82a6208/ht82a6216 rev. 1.30 92 january 14, 2011 2 8 1 1 5 1 4 a b c d f c ' g h a e
saw type 48-pin (7mm7mm) qfn outline dimensions asecl symbol dimensions in inch min. nom. max. a 0.031 0.033 0.035 a1 0.000 0.001 0.002 a3 ? 0.008 ? b 0.007 0.010 0.012 d ? 0.276 ? e ? 0.276 ? e ? 0.020 ? d2 0.219 0.222 0.226 e2 0.219 0.222 0.226 l 0.014 0.016 0.018 symbol dimensions in mm min. nom. max. a 0.800 0.850 0.900 a1 0.000 0.035 0.050 a3 ? 0.203 ? b 0.180 0.250 0.300 d ? 7.000 ? e ? 7.000 ? e ? 0.500 ? d2 5.550 5.650 5.750 e2 5.550 5.650 5.750 l 0.350 0.400 0.450 ht82a623r/ht82a6208/ht82a6216 rev. 1.30 93 january 14, 2011 d e e b a 1 a 3 a d 2 l e 2 k 1 1 2 1 3 2 4 2 5 3 6 3 7 4 8
44-pin qfp (10mm 10mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.512 ? 0.528 b 0.390 ? 0.398 c 0.512 ? 0.528 d 0.390 ? 0.398 e ? 0.031 ? f ? 0.012 ? g 0.075 ? 0.087 h ? ? 0.106 i 0.010 ? 0.020 j 0.029 ? 0.037 k 0.004 ? 0.008 l ? 0.004 ? a 0 ? 7 symbol dimensions in mm min. nom. max. a 13.00 ? 13.40 b 9.90 ? 10.10 c 13.00 ? 13.40 d 9.90 ? 10.10 e ? 0.80 ? f ? 0.30 ? g 1.90 ? 2.20 h ? ? 2.70 i 0.25 ? 0.50 j 0.73 ? 0.93 k 0.10 ? 0.20 l ? 0.10 ? a 0 ? 7 ht82a623r/ht82a6208/ht82a6216 rev. 1.30 94 january 14, 2011 3 4 1 1 1 4 4 a b 2 2 1 2 e f g h i j k a 3 3 2 3 c d l
52-pin qfp (14mm 14mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.681 ? 0.689 b 0.547 ? 0.555 c 0.681 ? 0.689 d 0.547 ? 0.555 e ? 0.039 ? f ? 0.016 ? g 0.098 ? 0.122 h ? ? 0.134 i ? 0.004 ? j 0.029 ? 0.041 k 0.004 ? 0.008 a 0 ? 7 symbol dimensions in mm min. nom. max. a 17.30 ? 17.50 b 13.90 ? 14.10 c 17.30 ? 17.50 d 13.90 ? 14.10 e ? 1.00 ? f ? 0.40 ? g 2.50 ? 3.10 h ? ? 3.40 i ? 0.10 ? j 0.73 ? 1.03 k 0.10 ? 0.20 a 0 ? 7 ht82a623r/ht82a6208/ht82a6216 rev. 1.30 95 january 14, 2011 3 9 4 0 5 2 1 2 7 1 3 a b c d 1 4 2 6 e f g h i j k
product tape and reel specifications reel dimensions sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 ssop 28s (150mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.20.2 ht82a623r/ht82a6208/ht82a6216 rev. 1.30 96 january 14, 2011 a c b t 1 t 2 d
carrier tape dimensions sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.850.10 b0 cavity width 18.340.10 k0 cavity depth 2.970.10 t carrier tape thickness 0.350.01 c cover tape width 21.30.1 ssop 28s (150mil) symbol description dimensions in mm w carrier tape width 16.00.3 p cavity pitch 8.00.1 e perforation position 1.750.1 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 10.30.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 ht82a623r/ht82a6208/ht82a6216 rev. 1.30 97 january 14, 2011 p d 1 w p 1 p 0 d e f t k 0 b 0 a 0 c i c p a c k a g e p i n 1 a n d t h e r e e l h o l e s a r e l o c a t e d o n t h e s a m e s i d e . r e e l h o l e
ht82a623r/ht82a6208/ht82a6216 rev. 1.30 98 january 14, 2011 copyright 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com

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